I don't fully understand this picture:
If the data and instruction caches are separated, doesn't that mean that this CPU is not von Neumann model but Harvard model?
And what does it mean that one cache is 2-way and one cache is 4-way?
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asked Dec 6, 2012 at 20:33
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1\$\begingroup\$ The "way"-ness of a cache refers to it's associativity. \$\endgroup\$– vicatcuDec 6, 2012 at 21:14
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2 Answers
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No, having separate caches does not turn a von Neumann machine into a Harvard machine; both caches still represent the same external memory. But separating the caches for instructions and data improves performance by preventing the two streams from interfering with each other.
The set-associativity, or "way"-ness of a cache is simply an indicator of performance (hit rate). It refers to the number of aliases for a particular cache slot that can be held in the cache before one of them needs to be replaced. In general, a cache with higher associativity will have better performance on most typical kinds of code, at the expense of requiring more complex control logic.
answered Dec 6, 2012 at 21:40
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1\$\begingroup\$ The associativity isn't an indicator of performance. Instead a higher set-associativity gives it better performance. \$\endgroup\$ Dec 7, 2012 at 0:35
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\$\begingroup\$ @Pacerier: Some subset of the memory address bits (usually LSBs) is used to select, or "index" a particular slot in the cache. The remaining address bits (usually MSBs, and called the "tag") can take on any value, and the set of memory locations that they represent are called "aliases" for that cache slot. \$\endgroup\$ Sep 19, 2017 at 11:05
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In a true Von Neuman architecture, if one instruction writes to the memory where the succeeding instruction is stored, that change should affect the next instruction executed by the processor. Such behavior was exhibited by many older Von Neuman processors like the 6502, Z80, and 68000. Many newer processors, however, including the original 8088, deviate somewhat from that model; some deviate more than others.
On the 8088, the execution of one instruction will in some cases overlap the fetching of succeeding instructions, such that by the time an instruction finishes executing, one or more following instruction have already been fetched. The processor makes no effort to detect this condition, but a branch or jump instruction will clear the prefetch buffer. Consequently, changes to code memory are guaranteed to be effective if a branch or jump is executed before the altered instructions. Such machines don't quite fit the Von Neuman model, but adding a jmp in the few cases where one wouldn't occur naturally is generally not a problem.
On some other processors (e.g. Motorola 68040), there is a code-memory cache which holds recently-executed instructions; if an instruction is in the cache, the contents of the corresponding main memory location, and any changes made to such contents, will be ignored if the instruction is still in cache the next time an attempt is made to execute it. Such processors often require that some explicit action be taken to clear the cache between the time an area of memory is written, and any attempt is made to execute code there. Such machines may be regarded as deviating significantly from the Von Neuman model, since the appearance of the secondary cache affects program behavior.
Today, the normal behavior is often to have separate code and data caches, but have some circuitry which detects when a memory location which is present in the code cache gets written. While it would be possible to simply update the code flash as appropriate to reflect the write, in practice it's often easier to simply erase the parts of the code cache which could hold stale data. Such situations don't occur terribly often, and the time spent handling them is seldom likely to be a significant fraction of overall execution time.
