I found the following question in a test. I am not looking for an answer to the question per se, but I am having difficulty understanding the part in bold, as explained below.
A main memory unit with a capacity of 4 megabytes is built using 1M×1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is?
As far as I know, an m x n memory chip has m rows of n cells each. Hence, the given chip should have 1M rows of 1 cell each. How come the bigger memory unit built out of it has 1k cells in each row?
What is the mistake I am making here? Is my understanding of the memory chip specification incorrect, or is there a way of reconfiguring memory chips to have more columns per row that I do not understand? Can someone please explain this to me?