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I'm curious to know, are there any differences between the assembly instructions of ARM MCUs from two different corporation? For example between an Cortex-M3/4 of NXP and TI or ST or other corporations.

Some of my friends say me that they have no difference. Is that correct?

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Core instructions should be the same. Peripheral instructions might vary. –  Ignacio Vazquez-Abrams Mar 21 at 17:20
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@IgnacioVazquez-Abrams What do you mean by "peripheral instructions"? The Cortex-M is a load/store architecture and there are no special instructions for I/O. –  Joe Hass Mar 21 at 17:23
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@JoeHass: I don't have much experience with the ARM instruction set, but as an example from a different architecture some AVR32 processors support DES and AES encryption in a separate peripheral with specific opcodes that are not listed in the generic AVR32 manual. –  Ignacio Vazquez-Abrams Mar 21 at 17:44
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Not sure when instructions shorter than 32-bits were introduced in the ARM core. There may be a difference too. –  jippie Mar 21 at 18:20
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Roh sorry to nitpick, but we use "is" when referring to a singular word (difference) but "are" when referring to multiple (differences). So the title and first sentence of the question are both correct even though they are not the same. (In one case asking "Are there any differences?" but in the other asking "Is there any difference?"). Confusing, pedantic perhaps, but that's why I edited it again. :) –  JYelton Mar 21 at 18:35

3 Answers 3

up vote 12 down vote accepted

I think the correct thing to say is that for a given architecture, such as the ARMv7-M architecture of the Cortex-M3 core, the instruction set is the same for all processors. However, the behavior of some instructions may vary because of implementation-defined (i.e. optional) functionality in the processor. Instructions that try to access optional capabilities that are not implemented in a particular processor may cause exceptions.

To find the features that may be implementation defined, search the appropriate ARM Architecture Reference Manual for IMPLEMENTATION, in all capitals.

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Also, timing may vary, depending on the speed of memories and buses. –  starblue Mar 23 at 8:21
    
@starblue The ARMv7-M Architecture Reference Manual specifies the execution time (in clock) cycles for the instructions, so the variation will be in clock frequency rather than at the instruction level. If you have a specific counterexample in mind, please tell us about it. –  Joe Hass Mar 23 at 13:11
    
I've programmed delay loops on LPC13xx and LPC17xx (both Cortex-M3), and LPC17xx is about twice as fast. Generally flash memory has wait states, while internal RAM doesn't, resulting in a factor of three slowdown for a 200MHz LPC43xx (Cortex M4). –  starblue Mar 24 at 19:37
    
Not trying to be argumentative but just curious...did the delay loops on the LPC13xx and LPC17xx involve memory accesses inside the loop or just register operands? When you say the LPC17xx is twice as fast to you mean real time or number of clock cycles? –  Joe Hass Mar 24 at 20:12
    
The memory accesses were just for the program if I remember correctly. The speed difference was in clock cycles, the actual difference was bigger because LPC17xx runs on a faster clock. I think on LPC17xx there is more effort to speed up flash access by prefetching and caching. –  starblue Mar 24 at 20:15

Processors within the same family (e.g. Cortex M3) should have the same instructions, but different families have different instructions. The original ARM used a set of 32-bit instructions, then a version appeared which could switch between "ARM" mode and "Thumb" mode, with the latter implementing a smaller set of 16-bit instructions. A job which takes half again as many Thumb instructions as it would take ARM instructions will take roughly half again as long to execute in Thumb mode as ARM mode, but will fit in 3/4 of the space.

Many newer processors do not have any 32-bit mode, but some can combine two consecutive instruction words in such fashion as to yield most of the instructions from the 32-bit ARM instruction set, plus a few more. Note that some 32-bit ARM instructions are not implemented. The net effect is that there is no processor which can perform every ARM instruction; different ARM families have different sets of instructions available to them.

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There a number of different variations on the ARM instruction set (see http://en.wikipedia.org/wiki/ARM_architecture for the details), and different vendors' parts might support different subsets.

Just as an example, there's no integer division instruction in ARMv6; it's optional in some versions of ARMv7, mandatory in others; and present in ARMv8.

Furthermore, a vendor making their own ARM-licensed CPU can in principle add or remove any instructions they care to.

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I doubt very much that ARM would allow a vendor to remove instructions and still call the CPU an ARM processor. Can you provide an example of this? I know it is technically feasible, I just doubt that it would be legally allowed. –  Joe Hass Mar 23 at 13:13
    
I don't have an example, but I don't see why ARM would care as long as they're getting paid, particularly in a closed embedded application. –  Russell Borogove Mar 23 at 18:25

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