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Frequency of a digital clock signal can be doubled by using an EXOR gate (clock at one input pin and delayed clock at another).

Can we use any similar circuit which can multiply frequency by three times ?

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Usually on a VCO (NE565) the multiplication of frequency obtaneid by a divider inserted between VCO output and the phase comparator. So to get fout=3x, a divide by 3 network needed (7490 4-bit binary counter). –  GR Tech Apr 1 at 11:35

3 Answers 3

up vote 8 down vote accepted

You can use a third harmonic filter (inductor and capacitor) to resonate at clk*3 and then a schmitt trigger inverter (or other gate) to turn the sine wave into a decent square wave at clk*3.

This works because a typical square wave has fundamental and odd harmonics in its spectrum: -

enter image description here

The blue waveform is the output from the tuned circuit when excited by a 1 MHz square wave. This can be magnified to logic levels with a comparator with a little bit of hysteresis.

Can we use any similar circuit which can multiply frequency by three times ?

I cannot tell you to believe it's similar but in my mind it is.

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The most common way it to use a PLL based frequency multiplier.

enter image description here Source (www.ee.ucl.ac.uk/~pbrennan/E771/PLL.ppt‎)

The Phase Locked Loop works for frequency of a signal (or more correctly -phase), like an op-amp works for Voltage. It has a high enough gain to keep the two inputs of the phase detector equal in frequency (and usually phase).

Applying a reference signal to the input, the other phase detector frequency becomes equal to the reference by virtue of the loop gain changing the frequency of the Voltage Controlled Oscillator (VCO) until the frequency error is zero and therefore the output frequency is Finput * N.

I've taken some liberties with the details like lock range, loop bandwidth etc.. but I hope you get the idea.

You may find it interesting that an XOR gate can be used as the phase detector in a Digital PLL frequency Multiplier:

enter image description here

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If one wants a clean 3x waveform with uniformly-spaced rising edges and a known timing relationship to the original, a PLL is the best way to go.

If one wants something with 3x as many rising edges as the original waveform, but doesn't particularly care how even they are, a simple approach is to use an oscillator that runs at least 6x the speed of the reference along with a counting circuit. As a possible implementation, have the 3x clock operate a three-bit counter a flop which captures the state of the reference, and a flop which captures the state of that flop. Have the counter jump to 000 any time the latter two flops read "01", and otherwise advance once per count whenever its value isn't 101. The LSB of that counter will pulse three times for each reference clock edge, provided that the input clock is fast enough for it to do so.

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