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When trying to drive a high capacitive load why do we gradually increase size of inverters in buffer design. Why not give the output of a circuit to one large inverter?

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About progressive sizing ? – BASIL VARGHESE Apr 2 '14 at 17:37
This question makes no sense without some context. – Olin Lathrop Apr 2 '14 at 17:40
This comes from VLSI design, where very small transistors are used in internal logic but they must ultimately drive very large transistors in the output buffers. – Joe Hass Apr 2 '14 at 18:21
@OlinLathrop I suppose you could take it that way, but at that point it seems like you're deliberately going out of your way to be confused. The information he provided does not make sense in the contexts you suggested, but it is sufficiently clear (and makes sense) for IC design. – W5VO Apr 2 '14 at 19:48
@W5VO: But IC design was never mentioned. Actually when I read the question, my first thought was inverters that make AC from DC, since I just had a recent questions about them on my mind. I'm not a IC designer, so the IC design context never occurred to me. If the OP had mentioned IC design, I would have no problem with this question and would have simply skipped it knowing it was not for me. – Olin Lathrop Apr 2 '14 at 20:01
up vote 3 down vote accepted

Let us assume that we have given the output to one large inverter. Now the signal that has to drive the o/p cap will now see a larger gate capacitance of the large inverter. This results in slow rise or fall times. A unit inverter can drive approximately an inverter that 4 times bigger in size. So we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64. So that each inverter sees a same ratio of o/p to i/p cap. This is the main reason behind going for progressive sizing......

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Driving a very large inverter from the output of a normal (tiny) logic gate means that a large capacitance will be charged and discharged with tiny transistors. This takes a very long time, causes slow rise/fall transitions on the output pin, and causes considerable power waste in the large inverter.

Depending on the exact process parameters, it usually turns out that the lowest total propagation delay results from having a sequence of inverters. As the signal progresses from the internal logic signal to the output pin the transistors in the inverters get larger, increasing by a factor of 3X to 5X in each successive inverter.

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+1. You might also mention that the method of logical effort can be used to calculate how many intermediate stages will give the lowest total propagation delay; typically a fan-out of 4 (FO4). – davidcary Apr 3 '14 at 13:36

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