When trying to drive a high capacitive load why do we gradually increase size of inverters in buffer design. Why not give the output of a circuit to one large inverter?
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Let us assume that we have given the output to one large inverter. Now the signal that has to drive the o/p cap will now see a larger gate capacitance of the large inverter. This results in slow rise or fall times. A unit inverter can drive approximately an inverter that 4 times bigger in size. So we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64. So that each inverter sees a same ratio of o/p to i/p cap. This is the main reason behind going for progressive sizing......
Driving a very large inverter from the output of a normal (tiny) logic gate means that a large capacitance will be charged and discharged with tiny transistors. This takes a very long time, causes slow rise/fall transitions on the output pin, and causes considerable power waste in the large inverter.
Depending on the exact process parameters, it usually turns out that the lowest total propagation delay results from having a sequence of inverters. As the signal progresses from the internal logic signal to the output pin the transistors in the inverters get larger, increasing by a factor of 3X to 5X in each successive inverter.