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I have given the image of Basys-2 board's power regulator IC and filters connected to it in schematic. This is just an example but this is pretty much a similar filtering design for most of the supply nets in most designs where you would see many many filter capacitors in parallel. My confusion is that why there is many many capacitors added in parallel rather than just one big capacitor in parallel. Can someone give me pros and cons of adding many many capacitors in parallel rather than one big capacitor for each supply net?

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does designer plan to locate these filtering capacitors to closest to the supply receiving ICs? –  dr3patel Apr 5 at 23:30
    
Most datasheets recommend one cap per device power pin. –  Connor Wolf Apr 5 at 23:56
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What a garbage way of showing the decoupling caps... –  Matt Young Apr 6 at 0:04
    
What @MattYoung said... –  bitsmack Apr 6 at 0:11
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It has become pretty typical in big multi-sheet designs with one big SOC as the main active component. The Protel (Altium) done this says Chinese designers to me. As to the OP, the speed of light is too darn slow to put the capacitance in one place. To provide current for sharp edged digital signals you put caps as near as possible to every place that switching takes place. –  C. Towne Springer Apr 6 at 3:07

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up vote 7 down vote accepted

Caps are located close to each digital IC, or small set of such ICs, to act as local reservoirs to smooth out the rapidly fluctuating current demands of such ICs. This prevents those rapidly fluctuating currents from causing fluctuating voltages on longer supply wires (PCB traces) and possibly disrupting other chips connected to those supply wires.

In some instances you will also see a large cap parallel with a small cap right next to it. The large cap provides a large reservoir, but has a significant internal resistance, so doesn't respond as quickly as a small cap can. So together the two caps can respond quickly and provide a large reservoir.

Real capacitors have both some internal resistance and inductance in series with their "ideal" capacitance. The effects are larger with larger-value capacitors, and vary with capacitor material and construction. For the current discussion, both these non-ideal characteristics act to slow the speed with which the capacitor can respond.

A good discussion can be found here: http://www.analog.com/library/analogdialogue/anniversary/21.html

An additional article on board layout for high-speed digital: http://www.ti.com/lit/an/scaa082/scaa082.pdf

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These caps are used as "decoupling" capacitors. Even though they appear like they're all next to each other, they will be located (often in pairs) on the circuit board next to power pins of digital IC's.

Unlike analog circuitry, a digital circuit uses power in short, fast bursts. All traces or wires have some inductance, which prevents the current from changing as quickly as the IC needs it. This causes two problems: The voltage fluctuates at the input pin, and the rapidly-changing current causes the traces to radiate electrical noise.

A decoupling capacitor provides two main functions:

  1. The first function is to prevent these two problems. It acts as a small power buffer right at the IC, and can provide the necessary rapidly-fluctuating currents. Since they are located right next to the IC's, there are no long traces to act as noise generators.

  2. The second function is to act as a filter, dampening noise seen from the outside of the chip. This is where the multiple values of capacitors come into play. The capacitors have some small parasitic inductance, also. Each capacitor you add creates an LC filter. Each different capacitor value, combined with the parasitic inductance, filters a different range of frequencies. It is common to see a 100pF next to a 0.1uF cap at each power pin. This combination has a favorable filtering bandwidth.

So, even though you could use one large capacitor to match the nominal bus capacitance, you would lose the decoupling benefits.

I hope this helps!

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This FPGA’s covers a broad range of frequencies at the range of 500KHz to 500MHz. So to keep flat the power supply impedance from msec to nsec, a parallel combination of capacitors of different values in a proper mix is used. The value it is not very critical and usually it is at the range of 0.001μF to 4.7μF, but the combination of values helps to keep the impedance low and to avoid resonance spikes (a value per decade for example) The low frequency capacitors (with higher ESR) and they have good performance in a wider range of frequency, so there is no need any combination. Typical values are from 470μF to 1000μF.

So it is normal to see as much as 50 capacitors in the footprint of an FPGA or around, like 1x680μF, 7x2.2μF, 13x0.47μF and 26x0.047μF

For further reading I can recomend this one

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