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The datasheet for the ATTiny13A, for instance, lists Min frequency of 0 MHz. Does this mean the clock can be run at any arbitrarily low frequency with no ill effects? I'm assuming it draws lower current at lower clock speeds? Does 0 MHz mean you can stop the clock completely, and as long as power is still applied, it will remember its state indefinitely?

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I would like to add, this is an excellent question. Most senior EEs do not take the time to actually read and think about datasheets, which is either a complement for you or an insult to them, I would like to imply both. –  Kortuk Dec 16 '09 at 6:44
    
I am not entirely sure that the internal RC oscillator is shut down unless you specifically instruct it to (through various power saving options). Not sure what it is used for, but at least for EEPROM and probably ADC. –  jippie Dec 18 '13 at 20:42
    
@jippie what internal RC you are saying? ATMegaX for example, has the internal RC for the system clock (normally 8Mhz, with optional div 8 prescaler), it has the watchdog oscillator. The system clock is fuse selected and is probably off when using external clock. The others as you said may be disabled by power-saving modes, but I doubt will stop by the system clock. –  Diego C Nascimento Dec 19 '13 at 0:57

5 Answers 5

up vote 54 down vote accepted

Yes. If the datasheet says "fully static operation", then you can clock it at any speed, even 0 Hz. A "dynamic" chip needs to have a clock at a specific rate or it loses its state.

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do you have an example of a micro that allows this? –  MrEvil Dec 16 '09 at 10:21
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Microcontrollers which contain on-chip flash may specify a minimum (and maximum) flash clock speed when writing to flash. However, when reading from flash, this doesn't apply. –  Steve Melnikoff Dec 16 '09 at 13:22
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MrEvil, the Atmel AVR ATtiny series mentioned in the question is fully static, as I think most all Atmel AVR chips. And I think most all of Microchip's PIC microcontrollers. –  todbot Dec 16 '09 at 17:56
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Actually, I think the ADC in the ATTiny13A doesn't work at low frequencies, maybe because of the sample-and-hold capacitor decaying? "By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. ... The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz." –  endolith Dec 17 '09 at 15:26
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endolith -- I agree, ADCs usually don't work at low frequencies. As far as I can tell, everything else on practically all modern microcontrollers continue to work fine all the way down to "0 Hz", aka "pause indefinitely". In particular, many microcontrollers have a "low-power sleep" mode that stops all clocks, until something -- typically a person pushing a button -- wakes it up and it resumes right where it left off. en.wikipedia.org/wiki/Static_logic_(digital_logic) –  davidcary Jun 15 '10 at 22:52

I am posting another answer, just because the last question you had was not answered before.

Todbot is completely correct. It will also draw lower power at lower speeds. It also means if you supply it's clock from another processor, for example, you could stop supplying it at any point and then start clocking it later, as long as you do not go faster than max speed, you will be fine.

The Chips I have get an order of magnitude change between 32768Hz oscillator and a 1MHz one. I have had applications where I did not need speed, I just needed another little guy doing some basic data handling for me.

Hope this helps.

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I've always wanted to run a microcontroller's clock line with a pushbutton. Let the human be the clock. :) On a serious note, a really nice things about these static designs is their power consumption is linear with clock speed: slow down the clock and use less power. This can be really handy. –  todbot Dec 16 '09 at 6:27
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Yes, but I do like to note, power consumption is a linear function with an offset, even without a clock they still consume power, especially with any outputs being driven. We just got new interns at my work, I will suggest we use a pushbutton and see what happens. –  Kortuk Dec 16 '09 at 6:39
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@todbot Nice idea. :-) But make sure to debounce the pushbutton. –  starblue Dec 16 '09 at 8:49
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Try with a "grind crank" (as in the Jargon meaning: jargon.net/jargonfile/g/grindcrank.html ) :-)) (and yes, many years ago I built one to step thru code when I was using Turbo Pascal at school :-) –  Axeman Dec 16 '09 at 9:19
    
@todbot It's not really far-fetched or difficult, if you can accept a rough abstraction. There are several examples of people using such gadgets to teach how computers work. Myke Predko has a really good book, and it even comes with PCBs (though not for the computer project): amazon.com/Digital-Electronics-Guidebook-Michael-Predko/dp/… –  Lou Dec 16 '09 at 13:41

Most modern microcontroller designs will work with any pattern on their clock input, provided only that no high pulse is below a certain minimum length, no low pulse is below a certain minimum length, and no low-high-low or high-low-high pulse pair is below a certain length. Essentially what happens is that after the chip does all of the actions associated with a particular clock edge, the chip will be in a state where it is doing nothing but waiting for the next clock edge. If the next clock edge doesn't arrive for ten days then (unless the chip has some external watchdog) the chip will be in the same state as if the edge had arrived the moment the chip was ready for it.

Note that in general, pausing the clock on a microcontroller will reduce current consumption substantially, but not as much as using the "sleep" feature. Most microcontrollers' current consumption in "run" mode can be pretty well estimated as a constant quiescent current plus a certain amount of current per cycle per second (which might be more 'naturally' expressed as charge per cycle). For example, a chip might have a quiescent current of 10uA, plus a current of 0.1mA/MHz (100pC/cycle). Running such a chip at 10MHz would yield a current of 1.01mA. Running it at 1MHz would yield 0.11mA. Running it at 100KHz would yield 0.02mA. Running it at 1Hz woudl yield 0.0100001mA. On the other hand, the chip might offer a sleep current of 1uA. Generally, entering sleep mode will completely power off areas of the chip that aren't going to do anything useful while the chip is sleeping, thereby avoiding any leakage current such areas might have. It will in some cases also reduce the voltage to areas like register files to a level where the register files can hold their contents, but not access them very quickly (since they won't be accessed at all, access speed doesn't matter).

Some older microprocessors, microcontrollers, and other devices had maximum clock-high and/or clock-low times. Such processors made use of dynamic logic to save circuitry. As an example of dynamic logic, consider a shift register: a typical static register bit requires a two-transistor circuit to hold the value, while a dynamic register bit holds the value on the gate of a readout transistor. A two-phase-clocked dynamic shift register may be realized in NMOS using four NFETs and two resistors per bit. A static shift register would require eight NFETs and four resistors per bit. Dynamic logic approaches are not nearly so common today. Back in the 1970's, gate capacitance was substantial and there wasn't any getting rid of it. There was thus no particular reason not to take advantage of it. Today, gate capacitance is generally much lower, and chip makers are actively trying to reduce it further. Making dynamic logic work reliably would often require deliberately working to increase gate capacitance. In most cases, the extra chip area needed to increase capacitance could be just as effectively used to add more transistors so as to make the capacitance unnecessary.

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You mention NMOS and IIRC there is a connection between the popularity of dynamic logic and complementary MOS (CMOS) not being available yet. –  jpc Apr 9 '11 at 21:13
    
@jpc: I've examined schematics of various NMOS chips--some in great detail, including the Atari 2600 TIA which is a real work of genius--people are still finding new things to do with it three decades later. I think one advantage of NMOS versus CMOS from a design-convenience standpoint is that 'shoot-through' (accidental simultaneous activation of high- and low-side drive) is a non-factor, though I'll confess some curiosity as to why CMOS isn't run at a low enough voltage that the cross-over point on an input would leave high and low side drivers off, rather than activating both. –  supercat Apr 9 '11 at 23:31
    
@jpc: In NMOS, it's possible to implement an XOR gate with two transistors and two resistors, if the inputs are sufficiently "strong". Even if one has to add inverters to both inputs, a four-transistor four-resistor xor gate would be better than many other approaches. I've never seen the approach used, though, even though I designed a similar circuit using BJT's around 1978 (the design concept would work better with MOSFETS, but I didn't know anything about them). –  supercat Apr 9 '11 at 23:34
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+1 - I feel like the real gem you mentioned here is that lower clock speeds do save power, but not as much as sleep modes which are specifically designed to optimize power savings. My gut tells me that you'll save more power running a fast oscillator combined with judicious use of sleep mode, over running at a really low frequency constantly. –  Joel B Jun 28 '12 at 14:02
    
@JoelB: That depends on many factors. On many processors, there is a delay between turning on a fast clock and being able to actually use it; during this time, one will waste power. If one would have to wake up e.g. 100x/second, it may be better to run slowly continuously than to be constantly starting and stopping. On the other hand, if one is going to be starting and stopping the fast clock, it may be good to minimize the amount of time that it's running to the extent one can do so without wasting additional energy. For example... –  supercat Jun 28 '12 at 14:54

Coming late to this question, it reminded me of a project I saw a while back.

It's a bat detector which uses a PIC running at zero Hz for most of the time, and is then clocked by the very signal it is detecting.

http://www.micro-examples.com/public/microex-navig/doc/077-picobat.html

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In this project the signal is both the clock and the power to the chip. :) –  endolith Apr 17 '13 at 13:38

Yes, you can stop the clock completely and restart it at a later time without consequences. You could even replace the clock by a pushbutton and go through your program literally step by step (frequency: about 0.1 Hz).

Power is almost linear with frequency: at 10 MHz the microcontroller will consume 10 times as much power as at 1 MHz. This does not mean that at 0 Hz the consumption is completely zero, though. There's always static dissipation, but that's very low, typically 1 uA or less.

PS: notice that the ADC does have a minimum operating frequency. If the frequency is too low the capacitor over which the voltage is measured will discharge too much and your measurement will be wrong.

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