The problem with your premise is that FPGAs are completely volatile* already. There is no special manufacturing step used to create FLASH/EEPROM, the "program" is stored directly in the Look-Up Tables (LUTs) where it is needed to perform your arbitrary logic. The LUTs consist of small SRAM arrays that are programmed, as well as some switch routing.
I know that at least Altera has a program where you can "hardcopy" your FPGA design, but this is a custom manufactured device, not something you can program in the field.
Now CPLDs have non-volatile memory, but you'll be unlikely to find an OTP (One Time Programmable) variant of a modern CPLD that already has an EEPROM/FLASH variant because it's not saving the manufacturer any (or enough) money. They already have a working chip with an IC process that has FLASH capability, and there probably isn't enough demand to justify the costs of a different memory element. That being said, there are definitely OTP CPLDs and PALs, but these are generally older parts when EPROM (UV erasable) was more common.
FPGAs are expensive because they're large (silicon-wise), require expensive, leading edge processes, have high pin counts, are low volume, and have a massive design software suite that they are subsidizing.
*most of them... I know there are some with non-volatile memory in them, but the core is still the same.