In case you are left wondering how the input resistance is spec'd as 100M, yet the impedance recommended driving for driving the input is 10k: The following diagram illustrates the input to the ATMega A/D:
As KyranF described, the task of your external circuitry is to ensure that the sampling capacitor CSH gets charged to a voltage that's within some percentage of the input voltage, within the sampling time. The charging process is slowed by the resistance of your voltage source, and by the resistance of the circuitry between the ADCn pin and the sampling capacitor, here shown as "1..100k ohm".
(That "1..100k" is a vast range, and I would be interested what the range actually is in practice.)
Not shown in the diagram are additional small capacitances associated with the multiplexer. And RAIN is also omitted, as it's insignificant compared to IIH and IIL (max 1uA).
The recommendation that your voltage source be less than 10k is essentially saying that we don't want the source resistance to slow the charging of CSH (and any other capacitances) significantly compared to the already present resistance, and relative to the sampling time. (However, the "1..100k" doesn't back that up very rigorously.)
Looking at this from another point of view, the supposed "100M" input resistance of ADCn pins is not the whole story. RAIN is parallel with IIH and IIL , which, when selected is also parallel with the "1..100k in series with 14pF" load.
In the sense that the 100M || IIH || IIL represent the entirety of the DC characteristics, it is legitimate, but it's not the relevant part of the load for our design purposes. We need to design to drive the "1..100k in series with 14pF" AC part of the load, which Atmel tells us is best done with a 10k source resistance.
(Note that in discussions the term "impedance" may or may not imply that non-resistive AC characteristics are expected, and is sometimes used where what is really meant is "resistance".)
[Edit -- cuz this turns out to be quite interesting...]
Adding some ballpark sample and hold settling times:
With R = 100k, and C = 14pF, the RC time constant (TC) is 1.4 usec.
For ATMega, the S/H time is 1.5 cycles of the ADC clock. For a midrange ADC rate of 100kHz, that puts the S/H time at 15usec. So that's a bit over 10 TC.
The voltage on a capacitor settles to within 37% of its final value in one time constant, 5% in 3TC, 1% in 5TC and 0.1% in 7TC (corresponding to +/- 1 bit of 10-bits resolution).
You can see that doubling the input R to 200k, or doubling the AD clock rate, will chew into the resolution. But a change of input R from 10k down to 1k doesn't do us much good... though it could be beneficial for external reasons, like lower sensitivity to neighboring noisy signals.
Hope that helps.