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To learn verilog, can anyone recommend any web-page or book?

I have never seen such type of a language before, so what you recommend should be for beginner.

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After trying to pick up verilog from online sources for a while, I finally decided to try VHDL instead. A lot of digital design courses around the world are taught using VHDL. This means that there is a wealth of information out on the Internet that is relatively good and readily accessible. Verilog, on the other hand, is more popular in industry where people are considerably less share-happy. I still utterly despise the VHDL syntax, but I found it a lot easier to get a working knowledge of it by using course material than I did with Verilog. – drxzcl Jul 25 '12 at 12:23
up vote 3 down vote accepted

I've recently embarked on a simmilar journey my self and so far I've found the following useful:

This youtube video blog by Tbird761 (http://www.youtube.com/watch?v=gsTpLtEEobE

and this book by Pong P. Chu (FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version [Hardcover])

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When I was learning Verilog I mainly used two resources, the Southerland Online Reference Guide and the FPGA4Fun website. Verilog (for me) required a massive brain shift, so take it slowly. You can do a lot of stuff in simulation, but sometimes it's difficult to create the test waveforms you need. Actually having an FPGA to program helps a lot. You should be able to get a simple board for ~$100. FPGA4Fun sells some useful boards.

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opencores.org is cool too. – user3045 Feb 28 '11 at 16:32

Probably the most important thing to understand about Verilog is that the tools you use to convert verilog (or vhdl) to gates have certain idioms that they use to map verilog to certain types of gates - you need to write using these to get what you want

As a (most simplest) rule:

always @(posedge clk) 
    q <= d;

will give you a flop while

assign w = a|b;

will give you a combinatorial (a logic net).

Understanding the differences between '=' and '<=' is important, but more important is simply making sure you use <= for all flops and = elsewhere.

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