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I found this design idea (Fast-settling-synchronous-PWM-DAC-filter-has-almost-no-ripple) on EDN where an RC integrator and a sample/hold amplifier are used to filter PWM signals into stable DC values.

schematic, figure 1

timing diagram, figure 2

From the schematics given in figure1 and results in figure2, it is clear that PT0 is the PWM signal to be recovered. What is PT1? not very clear. I think it is the time base for sample-&-hold. Is my thinking correct? And if so, then what is the relation between PT0 and PT1. The current schematic shows PT1 to be 50% duty. Does that need to change if PT0's duty goes beyond 50%?

Also, why does the author say that this DAC settling will take 0.1sec, when actually it should settle in 1 PWM cycle, so if my PWM frequency is 10KHz, the output should settle in 100us.

The chip used for analog switching is CD4053. This chip selection inputs S1, S2, S3 are active high, but the schematic in figure1 shows these inputs to be active low. Can we simply swap the signal inputs and achieve the same result?

Please enlighten me.

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1 Answer 1

up vote 2 down vote accepted

From the schematics given in figure1 and results in figure2, it is clear that PT0 is the PWM signal to be recovered. What is PT1?

It is a separate sample-hold control signal. It needs to have the same period as PT0, but it needs to have a fixed (50%) duty cycle and its rising edge must coincide with the falling edge of PT0.

Also, why does the author say that this DAC settling will take 0.1sec,

Actually, he says 0.01 sec, which is the PWM period he's using as an example (100 Hz from a 16-bit counter). If your PWM is at 10 kHz, you need to adjust R1 and/or C1 so that T2 is equal to 100 µs, and you will get one-cycle settling as well.

The chip used for analog switching is CD4053. This chip selection inputs S1, S2, S3 are active high, but the schematic in figure1 shows these inputs to be active low. Can we simply swap the signal inputs and achieve the same result?

Yes.

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From part1 of your answer, it seems that PT1 and PT0 must be complimentary outputs, but only one of them must have duty cycle control. That indicates at 2 independent OutputCompare pins on a dsPIC. Also one of them is then inverted...may be by using the 3rd analog multiplexer from CD4053 ? –  Vishal Apr 29 at 12:26
    
Then...whats the use of inverting the PWM twice...once against PT0 and then once for the sake of its orientation in schematic. –  Vishal Apr 29 at 12:38
    
Ok..looking at the schematic closely, it seems the blobs on the selector pins does not indicate a signal complement. those blobs appear even on Vout and Vref. So now complementing makes sense. –  Vishal Apr 29 at 12:40
    
Hi, It is getting extremely difficult for me to create the PT0 and PT1 signals as given above. I am using a dsPIC30F device. Two PWMs are created with independent duty cycle control, however, the duty cycle change happens by controlling falling edge, where as the above demands that PT0 must have fixed falling edge and variable rising edge...how to achieve that? –  Vishal May 7 at 9:42
    
Yes, this is why this technique isn't more widely used. There are generally better ways to do DAC at 10 kHz under most circumstances. It would be relatively easy to generate the two control signals if you were using an FPGA or CPLD. –  Dave Tweed May 7 at 11:02

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