Take the 2-minute tour ×
Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It's 100% free, no registration required.

I am trying to double my clock's frequency using only gates, flip flops or whatever but unfortunately I get a signal of which the duty cycle is far from 50%. Unfortunately I have to develop my system using FPGA but the chip I work with, does not support a PLL so before trying to work with another board I want to be sure that I cannot get the double frequency of my input clock. The input frequency of my system is 10 MHz and I want to make a signal of 20 MHz. I have done it using the attached circuit and I have also measured it but the duty cycle of it is not satisfying at all. Please I would appreciate if could someone suggest something that could be helpful.

Here is the circuit I have used.

Schematic

share|improve this question
add comment

4 Answers 4

I am trying to double my clock's frequency using only gates, flip flops or whatever

Start with a 20 MHz clock (that comes under the "whatever" umbrella) and reduce it to 10 MHz where it is needed using a flip-flop clock divider.

share|improve this answer
    
This is by far the best approach. –  Michael Karas May 12 at 14:34
1  
Unfortunately the only Input Clock Signal i have is 10MHz, which means that i cannot do many things except from trying to double the frequency.... –  user41498 May 13 at 8:04
1  
Why can't you get a 20MHz oscillator? –  Andy aka May 13 at 8:07
    
Because at my System i get only 10 MHz Input and it is the clock Signal that i have to use...Also it is used to for Video signals.... –  user41498 May 13 at 12:09
add comment

A PLL is generally required to achieve what you want to do. Trying to use just logic to do this requires the addition of some extra delays via R/C time constants to bring the 2x pulses up to near 50% duty cycle. However that will not generally happen inside an FPGA without bringing some signals to pins on the part where the R/C can be connected and then fed back into other pins. Another limitation is that such scheme will not be right on 50% duty cycle and for a given set of R/C values will only be useful at a particular narrow range of input frequency.

share|improve this answer
    
The original design had that Kind of ''analogue'' solution which in most cases is ok...The pll is the best idea but the fpga board from Altera that i have does not Support pll so before changing my fpga board to an fpga that has pll's i want to find out if there is a way to achieve it with gates and so on... –  user41498 May 13 at 8:08
    
Regarding the set of R/C of the R/C Circuit how do you calculate the values? –  user41498 May 13 at 12:07
    
You could approximate the R/C delay to be about 0.5 times the half clock period of the desired output clock. A starting point could be to use a value of delay=1.5*R*C where delay is in seconds, R is in ohms and C is in Farads. The 1.5 multiplier is just a starting point guess and is fully dependent on the FPGA's input logic level threshold levels. It is dependent to a secondary order on temperature, I/O pin propagation delays of the FPGA and symmetry of the low to high versus the high to low response of the FPGA input. The R/C would be connected to as a low pass (continued below) –  Michael Karas May 13 at 13:10
    
(Continued from above) filter - R in series from the FPGA output then C to GND. The common point of the RC connects back into the input to the FPGA. You need to drive the output of the FPGA with a copy of the lower frequency input clock (that hopefully has a 50% duty cycle). Then combine the delayed version of this clock at the input into your 2x circuit. –  Michael Karas May 13 at 13:28
    
If i got it wright you have written that : delay (sec)= 0,5*(1/2(0,05*10^-6)) where the 0,05*10^-6 sec is the period of the 20 Mhz (desired Output). If so, the next Thing is simply to test my board with These values' set. But something more...Is there a mathematical form or whatever to calculate the factor K=1,5: Multiplier which depends from some things?? –  user41498 May 13 at 14:26
add comment

Doubling the frequency can be as simple as this:

enter image description here

thanks to the gate propagation delay (I actually used this to overclock a TRS-80 when I was young).

Solving the duty cycle problem could be done (approximately) by changing the number of gates in series, but would only work for one frequency (and would probably be sensitive to components charateristics, temperature, etc.)

You could double the frequency twice and divide it once with a flip-flop to obtain a perfectly square signal, like Andy said.

share|improve this answer
    
You can also replace U2-U4 with a resistor, the input capacitance of U1 will form an RC filter... but would that still be "digital design"? –  hoosierEE May 13 at 0:02
    
Thanks a lot philfr! Unfortunately i make always that Kind of simulations using fpga and something like that cannot be simulated so i cannot go further with it... –  user41498 May 13 at 8:20
add comment

To cleanly double the frequency of an applied input clock would require a PLL, FLL, or other such circuit. Depending upon what you're trying to do, however, if you need to generate two clock events in response to an external clock stimulus over which you have no control, two approaches which I call "putt-putt-wait" and "putt-putt-skip" might be better.

For "putt-putt-skip", you need a free-running oscillator that runs more than three times (preferably more than four times) as fast as the input clock. Count how many pulses have been received on the input clock and how many have been output. On each clock from the local oscillator, latch the number of counts from the reference input, and output a pulse if the previously-latched count doesn't equal half the number of pulses output. Note that basing the output pulse on the previously-latched count will add an extra local clock's worth of phase delay, but will avoid any possibility of outputting metastable or "runt" clock pulses.

For "putt-putt-wait", you need an oscillator that can be started and stopped smoothly; the oscillator should run whenever the reference count isn't equal to half the number of pulses output, and stop whenever it is equal. If the oscillator can start and stop smoothly, this approach may yield a more consistent phase relationship between the input and output waveforms than would putt-putt-skip. It may also be more energy-efficient.

Both of these approaches will yield outputs whose phase relationship is not as clean relative to the reference wave as would be a PLL or FLL which has had time to acquire a lock. On the other hand, if the reference clock may be started and stopped, a PLL or FLL would require a certain amount of time to reacquire a lock each time the reference wave stops and restarts, and until the lock was reacquired its output phase would be essentially random relative to the input. By contrast, the putt-putt-skip or putt-putt-wait approaches will output a pair of pulses which follow within well-defined windows each input clock pulse received, regardless of whether those pulses form a continuous train, or periodically start and stop.

share|improve this answer
add comment

Your Answer

 
discard

By posting your answer, you agree to the privacy policy and terms of service.

Not the answer you're looking for? Browse other questions tagged or ask your own question.