Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It's 100% free.

Sign up
Here's how it works:
  1. Anybody can ask a question
  2. Anybody can answer
  3. The best answers are voted up and rise to the top

I'm trying to make a logic circuit simulation in Python. Currently i'm implementing a full adder. What bothers me is logic gates truth tables. I found out a full adder logic circuit schema:

enter image description here

and comparing it with truth tables found on wikipedia article:


Let's say this full adder gate have inputs: A = 1, B = 0 and Cin = 0. According to wikipedia article truth tables, the first HA (Half Adder) will output S = 1 and C = 0 (A and B are inputs). The second HA would have inputs Cin = 0 and the first's HA S = 1 which will again output S = 1 and C = 0. The OR gate will have two C = 0 inputs, which will of course output 0. So, the final answer should be Cout = 1, S = 0.

But wikipedia truth table for full adder says if A = 1, B = 0, Cin = 0, outputs are Cout = 0, S = 1.

Where am I making mistake?


share|improve this question
up vote 5 down vote accepted

Your mistake comes in your logic circuit schema. You have written s instead of c and vice versa. It should be as shown below:enter image description here

share|improve this answer

Your Answer


By posting your answer, you agree to the privacy policy and terms of service.

Not the answer you're looking for? Browse other questions tagged or ask your own question.