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I have a design in Xilinx system generator which meets maximum frequency of 50MHz (I found this from Timing and Power Analyzer of System generator). However, my FPGA board offers 100MHz clock rate. How could I solve this issue? (is there any way like creating a divided clock which can be assigned to the FPGA clock period of clocking options in system generator token?)

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Im not an expert on this but a little research (30seconds) on our favorite search enginge brought me to someone who had the exact same problem 5 years ago. I think you can go on from there, eventhough the frequency is a little different. http://www.velocityreviews.com/forums/t294219-frequency-divider.html

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