Take the 2-minute tour ×
Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It's 100% free, no registration required.

I have a design in Xilinx system generator which meets maximum frequency of 50MHz (I found this from Timing and Power Analyzer of System generator). However, my FPGA board offers 100MHz clock rate. How could I solve this issue? (is there any way like creating a divided clock which can be assigned to the FPGA clock period of clocking options in system generator token?)

share|improve this question
add comment

1 Answer

Im not an expert on this but a little research (30seconds) on our favorite search enginge brought me to someone who had the exact same problem 5 years ago. I think you can go on from there, eventhough the frequency is a little different. http://www.velocityreviews.com/forums/t294219-frequency-divider.html

share|improve this answer
add comment

Your Answer

 
discard

By posting your answer, you agree to the privacy policy and terms of service.