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I'm a newbie, playing around with a very simple single port block RAM (on an FPGA actually).

Its 'read'-timing is standard stuff -

i) An address on the RAM input gets latched on a first rising clock edge (call this edge 'one').

ii) Data stored at this address then appears on the ram output on the next rising edge ('two')

Now, obviously for step 'i' I need to make sure my address is set up and stable before (and for a hold-time after) rising edge 'one'.

My simple question is: what is normal practice for when to do this?

I could set up the address a full rising edge (edge 'zero') before its needed for latching at edge 'one' - but somehow this feels inefficient as it seems I'm taking at least 3 rising edges to get data out of my RAM.

Alternatively I could set up my addresses on the falling edge of clock, immediately prior to it being needed at rising edge 'one'. But I've read that using both rising and falling clocks in designs is also not an entirely typical approach.

What's best? Have I misunderstood something basic?

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1 Answer 1

up vote 4 down vote accepted

FPGA's are generally designed with 0 hold time.

That means you can set up the address on clock cycle #1, and the RAM will output the desired data in cycle #2. If the address changes on the transition to cycle 2, it won't violate hold time (because min hold time is 0).

I could set up the address a full rising edge (edge 'zero') before its needed for latching at edge 'one' - but somehow this feels inefficient as it seems I'm taking at least 3 rising edges to get data out of my RAM.

This is basically what I'm saying to do.

There is a latency of 2 cycles to set up the address and read the output, but the troughput is potentially one read per cycle, because you can change the address every cycle and get new data out each cycle.

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That's really helpful Photon. Thanks for the answer –  Walloon Jun 4 at 7:13

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