# VHDL: integers for synthesis?

I'm a bit confused on if I should be using integers in VHDL for synthesis signals and ports, etc.

I use std_logic at top level ports, but internally I was using ranged integers all over the place. However, I've stumbled across a few references to people saying you should only use signed/unsigned for synthesis-targeted code.

I've gone and reworked my current project to use unsigned... and, well, it's noticeably uglier.

Is it a bad practice to use integers? What's the problem? Is there some uncertainty on what width the tool will map integers to?

-
 Good question. I've been wondering that myself. I started with using integer, positive and other types all over the place but it turned out to be very hairy to get synthesized properly. I'm hoping someone can explain why everyone ends up using std_logic in a highly typed language. – trygvis Mar 21 '11 at 8:55 Yeah. Isn't that crazy? Highly typed in current practice tends to result in a lot of DATA_I <= TO_UNSIGNED(32010, DATA_I'LENGTH); type stuff... that doesn't bother anyone? :) It sure seems like a lot of unnecessary baggage. (Especially when adding STD_LOGIC_VECTOR() to that) I've declared my type and size, this should be DATA_I <= 32010; That should be implicit. Going between signed/unsigned, etc can and should be be explicit... but a straight unambiguous assignment or operation on integers should be implicit. – darron Mar 22 '11 at 14:33

Integers are fine in synthesis, I use them all the time.

I use std_logic at top level ports, but internally I was using ranged integers all over the place

That's fine!

Be aware:

• You are simulating first aren't you :) - Integer types don't automatically "roll-over" in simulation - it's an error to go out of the range you've specified for them. If you want roll-over behaviour, you have to code it explicitly.
• They are only specced to go from $-2^{32}-1$ to $+2^{31}-1$ (i.e. not quite the full range of a 32-bit integer, you can't use $-2^{32}$ and remain portable), which is a bit of a pain at times. If you need to use "big" numbers, you'll have to use unsigned and signed.
• If you don't constrain them, you can sometimes end up with 32-bit counters where less would do (if the synth and subsequent tools can't "see" that they could optimise bits away).

On the upside:

• They are much faster to simulate than unsigned/signed vectors
• They don't automatically roll-over in simulation (yes, it's in both lists :). This is handy - for example you get early warning that your counter is too small.

When you do use vector types, you are using ieee.numeric_std, not ieee.std_logic_arith aren't you?

I use integers where I can, but if I explicitly want "roll-over n-bit counters", I tend to use unsigned.

-
 Yes, I use numeric_std. I guess I'm mostly worried about Xilinx tools... they still generate std_logic_vector for everything and "UNSIGNED" isn't even in the syntax highlighting. – darron Mar 21 '11 at 15:54 @darron Don't worry about the syntax highlighting. The editor and its syntax highlighter are a completely different piece of software from the synthesis tool. Also, unsigned is "just" a datatype. It is part of a standard library, not of the language itself. – Philippe Mar 30 '11 at 11:22

Jan Decaluwe wrote an entire white paper on the problems of integers versus bit vectors. I expect his answers would be to use integers whenever possible. http://www.jandecaluwe.com/hdldesign/counting.html

-