I'm a bit confused on if I should be using integers in VHDL for synthesis signals and ports, etc.
I use std_logic at top level ports, but internally I was using ranged integers all over the place. However, I've stumbled across a few references to people saying you should only use signed/unsigned for synthesis-targeted code.
I've gone and reworked my current project to use unsigned... and, well, it's noticeably uglier.
Is it a bad practice to use integers? What's the problem? Is there some uncertainty on what width the tool will map integers to?