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I'm (again) placing bypass capacitors around an FPGA, and can't seem to get to a sane solution, given that I have all the pins assigned, and the supply pins are right in the middle of the I/O pins.

As an example, placement around pin 1:

Bypass Capacitor Placement

The next pin is another supply again (I can manage that, but I get further and further away), then a few I/Os, then another supply of the high ripple kind right in the middle of the package side.

So far, an avenue I haven't yet explored is shrinking the footprint (I use the standard 0402 from Eagle, which are humongous), and I'm wondering whether I can sensibly do so, and how big I need to leave the SMD pads in order to keep a strong connection.

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3 Answers 3

I put bypass capacitors on the back ("solder") side of the board, inside the chip outline, with the vias inder the chip - that keeps them out of the way of the signal lines.

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That's what I did. –  Naz Jul 7 at 21:52
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Massively increases the production costs though if you're getting it fabricated. Double-sided loadouts are costly. –  Majenko - not Google Jul 7 at 21:52
    
@Majenko given that he already has via, he must have at least 2 sided board. –  Naz Jul 7 at 21:54
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@Naz I don't mean copper on both sides - I mean components on both sides. Placing those components in a production situation (factory) is much more expensive than just having them on one side of the board. –  Majenko - not Google Jul 7 at 21:55
    
Yes, that is plan B -- however I have ~150 components in 0402 packages, so I'd definitely like to keep an eye on automated production in the long run. –  Simon Richter Jul 7 at 22:04

The IPC-7351 (2005) document attempts to standardize component footprints. Manufacturers are not compelled to use the standard, but more and more of them seem to be doing so.

In Section 1.4 of that document, they talk about Density Levels ("Most", "Nominal", and "Least" protrusion). This refers to how much the land patterns will protrude from the actual point of connection.

Reducing the land pattern protrusions will allow you to pack parts in more tightly, but make it more difficult to get a good solder connection. For example, with Density Level 3 (Least protrusion), there isn't enough pad to hit with a standard soldering iron tip. Unless you're really good, you have to reflow them.

For an 0402 component, these are the recommended values for Nominal and Least Protrusion density levels:

Nominal enter image description here

As you can see, there's quite a difference!

I took these screenshots from a software called Library Expert. It's free, and quite useful. It creates footprints to the IPC-7351 spec. It will actually build up the symbols for a number of software packages, e.g. Eagle, OrCAD, Altium, and others.

Good luck!

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Sometimes the FPGA manufacturer recommends a fanout pattern and capacitor placement pattern. Have you looked at the datasheet for the chip you want to use for capacitor placement information? Have you looked at development boards that use that chip?

Often when doing PCB layout I cram all the parts on the board. Then later -- when laying the traces -- I find out I don't have enough room between the parts to run all the wires.

In particular, fine-pitch components like TQFPs need a lot of room around them to "fan out" their wires, sometimes more room than I expected. (PCB layout artists find it requires even more resources to fan out BGA packages).

I generally end up spreading the wires apart something like this, to give myself plenty of room for capacitors and via patterns and other kinks in the wires between the components:

enter image description here

(image from FPGA-Based Retrocomputing http://www.fpgaretrocomputing.org/pdp10x/ )

I typically end up with capacitors on the same side of the board as the chip, with the +VDD end of the capacitors pointing directly at the chip, and the GND end of the capacitors pointing away from the chip, as in figure C of " Best place to place a decoupling capacitor ". Occasionally I end up with capacitors on the same side of the board as the chip, with the capacitors going "across" the fanned-out traces, as in C19 in the top image at " Decoupling caps, PCB layout ". (But as I said before, more often like C17 in that image).

This generally means capacitors left and right of the chip are horizontal, while capacitors above and below the chip are vertical. However, sometimes it is convenient to have capacitors near the corners placed diagonally, like several of the capacitors connected to pins near the upper-left corner of this Xilinx FPGA:

enter image description here

(from http://www.summitsoftconsulting.com/UsbAnalyzers.htm ).

Some BGA packages force us to put capacitors on the opposite side of the board, directly underneath the chip, as described by Peter Bennett. Since I haven't yet used such high-density BGA components, I find that keeping all the surface-mount components on the same side of the board typically reduces costs.

I personally find it much easer and takes less time to

  • leave more space than I really need around TQFPs, and later squeeze everything together, rather than

  • pack components closely, and repeatedly discover that there's not enough room for the traces, so each time I nudge the components a little further apart.

There are a few cases where bigger capacitors make it easier to lay out the PCB. When a package has an I/O line, then a VCC line, then an I/O line, then a GND line, then another I/O line -- a bigger capacitor can make a "overpass bridge" from the VCC to the GND line, and the I/O line can run underneath the capacitor, something like C65 and C61 in this photo:

enter image description here

(image from http://veriest-v.com/index.php?id=16 )

Good luck!

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