# 74154 4 to 16 decoder logic diagram

Will someone please explain the purpose of inverting the outputs (0 through 15) as well as the use the NAND gates here?

2nd, less important question: why are there two input G1 and G2 if the technical specs for this DIP states that all inputs (a,b,c,d) are only considered when both G1 and G2 are low, and than when either (or both) G1 and G2 are high, all inputs are "don't care" ?

My first question is more important... 2nd is just my observation that I wonder about.

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First, the inversion of the outputs simply means that the output is active low. That is, for an input of 0000, the 0 output is selected, and it is driven low. All the other ouputs stay high. The NAND gates are used because, given that the active lines on the 74154 are low, DeMorgan's Theorem allows NAND gates to function as OR gates. That is, if the 74154 outputs were active high, OR gates would perform the synthesis desired. Since the ouputs are active low, NAND gates do the job.

The active-low enable inputs allow cascading of demultiplexers over many bits. If you wanted to generate a 1 of 256 demultiplexer, you could use 16 74154s looking at the 4 least significant bits, while a single 74154 would look at the 4 most significant bits, with one ouput going to each of the other 16 74154s. And why are there 2 of them, you ask? It's because with a 24-pin package, 2 power pins + 4 address pins + 16 output pins = 22. Rather than providing only a single enable, both pins are used. This allows more flexibility in the logic functions available.

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Thank you. I remember now that inverting the inputs on a two-input NAND gate is the same as an OR gate. – asdf Jul 9 '14 at 1:24
Hey, @eestack. Please consider upvoting those questions you found useful (like this one) by clicking the arrow pointing up near the answer vote count (which is in turn above the checkbox you clicked to accept this question). The person who took time to answer the question will appreciate that. You can upvote more than one answer. Thanks!! – Ricardo Jul 9 '14 at 1:41
@Ricardo Thanks. I am a new user so I didn't know I had that power. – asdf Jul 9 '14 at 3:47

The active-low output is just how the design for that specific decoder was carried out - there is also active-high varieties.

As for the NAND gates, there is a function being implemented in which the gates are there to realize it. For instance, f1, will be LOW (because all non-selected outputs are HIGH) unless the decoder selects output 2, 4, 10, 11, 12, or 13 which will cause the output to drive HIGH.

If you want to know exactly what is going on then draw out the truth table, but it is unlikely their function will make much sense to you.

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Thank you. ----- – asdf Jul 9 '14 at 1:28

Many TTL parts and older memory chips have active low enable inputs, so the active low outputs of this part can be connected directly to those inputs.

There are probably two enable inputs because otherwise there would be two unused pins on the 24 pin package (I don't recall seeing 22 pin DIP packages).

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Thank you. So is it possible that both enables are hooked to a 2-input OR gate; this is just making use of the extra pins to make 24? – asdf Jul 9 '14 at 1:27
According to the internal logic diagram on the 74154 datasheet, the G inputs are connected to a two-input AND gate with inverting inputs, whose output feeds one input of all the NAND gates that produce the outputs. – Peter Bennett Jul 9 '14 at 1:56