I'll start off by saying that you appear to be taking care of a few things correctly. Controlling edge rates(resistors), adding a buffer/driver (745402) etc.
Well you can probably rule out the ADC internal workings, Analog is an excellent company, they know what they are doing and they've sold lots of those devices, and I've used these devices in this exact application with good results.
Now for the constructive criticism.
The ADC is a very sensitive device (wide BW and high level of conversion) you have to be careful.
- for these applications I typically run dedicated LDO's, filters before (Pi filters with L's and C's) and after for the buffers and the ADC's - all separate.
Clock driver for ADC:
- rail bounce on the clock source manifests itself in jitter on the sampling aperture which manifests itself in MSB counting noise. - separate power supply and driver form the clock. The SGL (Single gate Logic) is your friend.
Layout - Layout and yet again layout:
- Is very important. BE aware of image current flow, the return paths of the signals that are running to the buffers. Ground plane splits etc. etc.
Some more obscure things:
- some resistor packs are nasty, additional inductance and cross -coupling capacitance. It wouldn't necessarily affect your results here. I tend to use individual resistors (0402)
As per DaveTweed excellent observation (re timing skew) one solution is to replace the buffers in your schematic with D ff's /latches to reclock the data and buffer it at the same time. I normally do that and Dave's comment reminded me.
After update (comments about clocking);
I never, ever , ever allow FPGA, CPLD inputs into an ADC. I either run a separate clock source or if I have to have a specific clock frequency that is generated, I reclock using SGL's (D FF's) at a higher frequency (paying attention to setup and hold times of course). The reason for this is that the structure of FPGA's and CPL's causes a lot of power rail sourced jitter in the timing of the outputs from these devices. This jitter in turn interacts with the sampling window of the aperature period of the ADC front end causing noise problems.