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Suppose I have some sensitive proprietary software (VHDL/Verilog) on an FPGA connected to my server so I can control it by SSH. Now suppose an attacker compromises my server and can communicate with the FPGA. Could the attacker read the sensitive software off of my FPGA?

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What do you mean by "connected to your server"? Are you talking about the JTAG port or are you talking about being connected through logic that is configured by how you program your FPGA? –  placeholder Jul 20 at 22:56
    
It is connected using serial directly to the FPGA logic –  René G Jul 20 at 22:57
    
A bit more details on your setup could have brought more specific answers to your question. It heavily depends on which vendor and which parts you are using, how you are programming the FPGA, etc. –  strnk Jul 21 at 1:15
    
@strnk The question was more hypothetical than immediately practical –  René G Jul 21 at 4:59

2 Answers 2

up vote 7 down vote accepted

The bitstream that controls the functionality of your FPGA is normally called the "configuration", not the "software". The configuration bitstream is generated by using FPGA synthesis tools to compile the Verilog/VHDL source code.

There are a number of different ways that the configuration can be transferred into the FPGA each time it "boots up". Roughly, they are:

  • The configuration can be loaded directly by the development system via the JTAG interface.
  • The configuration can be auto-loaded by the FPGA itself from an attached EEPROM device. The EEPROM device is itself often programmed via the JTAG interface as well.
  • The configuration can be loaded by your server's CPU from a disk file.

If an attacker gets control of your server's CPU, then obviously he can read the disk file if the third setup is being used.

If the server's CPU has a direct connection to the FPGA's JTAG interface, then the attacker could read the FPGA configuration either directly from the FPGA, or indirectly by reading the EEPROM device.

In a security-sensitive application, you'll want to use the second setup, with the FPGA reading the configuration from EEPROM, and you'll want to make sure the server CPU does not have access to the FPGA/EEPROM JTAG port. Obviously, you won't store any of the FPGA Verilog/VHDL source code on the server, either.

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Even with the full bit-stream read off the FPGA an attacker would need a lot of resources and time to reverse-engineer your software. Most, if not none, vendors doesn't release their architecture specifications regarding the bitstream (i.e. which part configures what in the FPGA). Additionally, bit-streams can be encrypted on the disk and decrypted on-the-fly by the FPGA (e.g. with Xilinx), which would render point 3 rather useless anyway if the attacker doesn't have direct access to the FPGA platform. That's how most non-royalty-free IPs are distributed. –  strnk Jul 21 at 1:14
    
@strnk: No, encryption of IP and encryption of configuration bitstreams are completely separate issues and different mechanisms. But you are correct that reverse-engineering is very difficult if not impossible. However, that may not be an attacker's goal; they may just want to perturb the operation of the system in some way. –  Dave Tweed Jul 21 at 1:51
    
I know that IP and bit-stream encryption are separate issues, I just wanted to make a parallel since the final goal is equivalent in both case: you want to be able to distribute your belonging without letting unauthorized people to have a usable access to it. Hardware AES crypto-cores usable for bitstream decryption are more and more included in mid-range to high-end FPGA parts to specifically answer this kind of use-case where you don't control who have access to the bit-stream. As you point out the different weaknesses of the OP setup you could also provide ways to fix them. –  strnk Jul 21 at 1:59

Unless the attacker can reprogram the logic, read the flash/eeprom/boot rom or access your programming files on the computer the answer is no. There really is no way to fully determine the switch settings in the layer of cells that contain the configuration setting unless you have direct access to them through the JTAG / programming port.

You may be able to infer some settings in some situations but you'd barely scratch the surface.

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Actually, many modern FPGA families do have internal interfaces between the FPGA "fabric" and the configuration logic, to support features such as dynamic reconfiguration. If you're building something for a security sensitive application, you need to take that into account. –  Dave Tweed Jul 20 at 23:17
    
@DaveTweed Many? That word many does mean what you think it means. Altera doesn't have anything that I can find and Xilinx only has partial reconfigurability in some of the devices (which has to be preconfigured and is limited). xilinx.com/tools/partial-reconfiguration.htm . –  placeholder Jul 21 at 3:15

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