can I write into a previously-written page, if I avoid the
If I understand p. 16 of the datasheet correctly, it is saying: With this particular chip, you must not write into a previously-written page, even if you avoid the already-written areas.
The SST25VF064C flash memory chip datasheet on p. 16 says "The page-Program instruction programs up to 256 bytes of data in the memory. The selected page
address must be in the erased state (FFH) before initiating the Page-Program operation."
I assume that therefore "The entire selected page must be in the erased state (every byte on the page FFh) before initiating a Page-Program operation." Has SST or Microchip released any documentation clarifying this maddeningly ambiguous sentence?
In my experience, the manufacturer of all MLC flash chips and some newer SLC flash chips mandates that once a page has been written, the page must be erased before that page is written again, even if you only want to change some 1 bit to a 0 bit.
(This is called the "write-once rule" in the YAFFS article.)
In my experience, all of the older flash chips allow you to change any 1 bit to a 0 bit without an erase cycle, even if that bit is in a page or even a byte that has already had other bits programmed to zero -- a page of flash can be programmed multiple times between erases.
(This is called "multiple-write" in the YAFFS article).
The manufacturer's datasheet is a conditional promise the manufacturer makes to you. As long as you follow all the datasheet recommendations, the manufacturer promises that the chip will operate as specified.
I suspect that if you program a previously-written page, avoiding the already-written areas, there is a good chance than an immediate read-back might give the data you expect -- the newly-written bytes are the values you just wrote, and the other bytes are likely unchanged.
However, because this doesn't follow the datasheet recommendations, you can no longer rely on all the promises in the datasheet. I hear rumors that such non-sanctioned activity causes data retention time and endurance to suffer,
because of program disturb, over-programming, charge trap, effects similar to DRAM row hammer, etc.
"The memory use scheme influences the bit error rate. Partial-page programming, non-sequential pages programming within the block, excessive read per block without erase as well as non-equal number of read operation within a single block increase number of the read disturb errors."
-- Michal Jedrak.
"NAND Flash memory in embedded systems".
"Program disturb occurs when a bit is unintentionally programmed from a “1” to a “0” during a
page-programming event. This bit error may occur either on the page being programmed or on
another page in the block. Bias voltage conditions in the block during the page programming can
cause a small amount of current to tunnel into nearby memory cells. Repeated partial page
programming attempts will continue to aggravate this condition."
-- Douglas Sheldon and Michael Freie.
"Disturb Testing in Flash Memories".
p. 8, 9.
"Program disturb happens when a bit is unintentionally programmed (1 to 0) during a programming operation. ... This condition is made worse by random programming in the block and by applying multiple partial writes to the pages."
"Yaffs NAND flash failure mitigation"