Bypass capacitors needed in low-frequency digital logic systems?

Question

I know it's good practice to use bypass capacitors near the power pins of your ICs, but I'm now moving on from the breadboarding stage to the PCB-design stage, and I'd like to know if there are any good rules of thumb for when the caps are actually needed (I don't want to waste any PCB real-estate).

For example, what if I have a simple counter IC fed by a 250KHz clock signal? 31.25 kHz? If all input and output signals of an IC are changing at sufficiently low frequencies and if the IC doesn't draw much current, can I leave off the bypass caps?

Edit: inserted text in italic.

Answer 1

The relevant factor is the rise/fall times, not the clock rate. Here is a relevant paper. Conventionally, designers stick to 100nF cap per IC. Bear in mind that they serve multiple purposes: signal integrity, power supply noise, internal IC operation, radiated EMI, susceptability to EMI. Using an SMT 0805 or smaller (smaller is better) shouldn't take too much board space.

Answer 2

When, in the distant past, I used to do discrete logic designs, the rule was to put a 100nF ceramic by each chip and one 47uF electrolytic for every 6/8 devices. This was in the days of 74LS ttl and 16MHz 80386 processors.

Answer 3

When it comes to decoupling, clock frequency is rarely what determines how to do it. The primary determination on simple chips (like quad-gates, buffers, etc.) is the edge rate (or slew rate) of the output signals. The faster that signal transitions from 0 to 1 and 1 to 0 is the edge rate. The faster the edge rate the more decoupling caps are required.

Edge rate is still very important for complex chips, but the logic inside the chip becomes a significant factor too. Essentially, there are signals inside the chip that are transitioning too, and although you can't see or probe them they are important.

Decoupling caps are important, don't skimp on them-- especially when your power distribution wiring has more impedance than you'd like, as in a breadboard.

Answer 4

My inclination would be to assume that if a chip does not have a bypass cap, the outputs and internal state may be arbitrarily randomized for a few nanoseconds any time any of the inputs or internal state changes. If this would cause adverse effects, use a bypass cap. If this would not cause any adverse effects (e.g. because the outputs of the chip will only be sampled at a time long after the inputs have changed, and because the input changes are sufficiently far apart that output noise would not cause unwanted RF emissions) then the bypass caps may probably be omitted. Note that by this definition almost any part with any sort of latching will need a bypass cap; if the state of a device's output pins will always either be irrelevant to any downstream circuitry or else be determined unambiguously by the inputs, any latching will be irrelevant.

Answer 5

The reason that capacitors are placed between IC supply pin(s) and power return (ground) is usually to filter out noise produced as current pulses are sucked into the IC (sorry if I'm stating the obvious). This is mostly a consideration with digital ICs, not so much with say linear amplifiers. CMOS digital circuits, for example, generally only draw current when they switch. Thus, the supply current tends to go in pulses. These current pulses create voltage noise as they flow through the finite interconnect resistance between the power supply and the IC. Additionally, the power supply (or battery) will generally have a finite output resistance which will have a voltage drop across it as current is pulled from the power supply. And since many circuits usually share a supply, everybody sees this noise -- not a good thing for sensitive circuits.

However, with a "local" filter (decoupling) capacitor placed right at the IC supply pin, most of the current pulse will be pulled out of the local capacitor and will not need to come from all the way from the power supply. And since the pulse is brief, the total charge taken out of the cap will be small enough that the capacitor voltage will droop only a little bit--so not much current will need to come from the supply to charge it back up over each switching cycle. Upshot: noise on the supply rail is greatly reduced.

As others have suggested, the clock frequency is not so much the problem. The amplitude of the current spikes is the problem. The more transistors switching, the more current will be drawn. And since the transistors switch very quickly, the current pulses will be very brief (this is sort of what is meant when talking about edge rate or slew rate). You could imagine a situation where many many transistors switch synchronously at 10Hz and draw gigantic current spikes. So indeed, clock rate does play a large part, but not the only part.

Decoupling is primarily an issue with digital ICs, but you do generally want to use decoupling caps on the rails of say an opamp as well, since it will help filter out noise produced by other circuits.

Updated: generally the rule of thumb would be to stick a 0.1uF on each power pin. Shouldn't take up too much space. Even if the RMS current is low, the pulsed current could be higher. But if you have a noise-robust system (all digital, few components, low power, low current), it may not really matter much...

Answer 6

What drives your concern about PCB real-estate? 0.1 uF and 1 uF caps are physically small, and usually adds only small routing complication.

Doing surface mount devices? Try adding the caps on the back side of the board.

Doing socketed-DIP's? You can get sockets with built-in capacitors, so you could design without the caps, and change your socket if you find that you need them.

Answer 7

I do not think so. 250kHz is not low frequency as far as PCB layout and decoupling is concerned. You do not need electrolytics on every chip, a \$1\,\mathrm{\mu F}\$ SMD ceramic should have you covered.