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Below is an ac-coupled emitter follower with base bias provided by a voltage divider. I'm having a slight issue with how the resistor values are chosen for the biasing in the design example provided in the Art of Electronics (pg 70). I've included the design steps given in the book up to that point.

enter image description here

Step 1. Choose VE. For the largest possible symmetrical swing without clipping, VE = 0.5Vcc, or +7.5 volts.
Step 2. Choose RE. For a quiescent current of 1mA, R E = 7.5k.
Step 3. Choose Rl and R 2 . VB is VE+ 0.6, or 8.1 volts. This determines the ratio of Rl to R 2 as 1: 1.17. The preceding loading criterion requires that the parallel resistance of Rl and R 2 be about 75k or less (one-tenth of 7.5k times h FE ). Suitable standard values are R 1 = 130k, R2 = 150k.

In step three, it says the Thevenin equivalent of the voltage divider used (R1//R2) should be at least ten times less than the apparent resistance of the load resistor RE (RE * hFE). However, I think that instead of the Thevenin equivalent, we should only consider R2, since R2 is effectively in parallel with the load resistance * hFE. If we don't, then won't the loading effect on the voltage divider be too great?

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5 Answers 5

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Looking into the base terminal we see the equivalent of a resistor of value Re *hfe, so if hfe is 200, it looks like a 1.5M resistor to ground.

They are saying we can ignore that if R1 || R2 << (Re * hfe), where they consider an order of magnitude to be close enough- so a reduction in swing of Vcc/20 is considered insignificant. There's nothing stopping you from correcting the ratio a bit to account for typical hfe, but when AoE was written 5% resistors were much cheaper than 1% and it didn't matter that much.

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That's where I am confused. Since we see a resistance of RE *hfe looking into the base, that resistance would be in parallel with the the resistor R2. Since R2 is 150k and the equivalent resistance is 750k (hfe = 100), would that not load the divider? –  Ammar Aug 11 at 12:09
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@Ammar: A lot of answers and a lot of comments. However, I am not quite sure if the following was clearly stated already: The input resistance at the base is r1=rbe+betaRe (or: r1=hie+hfeRe). That means: The overall input resistance of the whole circuit is r,in=r1||R1||R2. That´s the whole story. The question why the divider circuit should provide a "stiff" voltage was answered in my detailed answer. –  LvW Aug 11 at 14:34
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@LvW As Ammar has correctly observed, r1||R1||R2 is not quite the whole story since r1 is not really in parallel, there's a Vbe drop in there. It's only in parallel in the small-signal approximation. In this case we're talking about less than 1% effect on the bias (10% of 10%), but I think it's sloppy thinking, especially for a beginner, to outright ignore it. –  Spehro Pefhany Aug 11 at 14:40
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Yes, that's correct. They ignore the loss due to the source resistance since it's not very large. This is not about optimizing the design, just getting reasonably close. –  Spehro Pefhany Aug 11 at 17:05
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Ammar - OK, perhaps there was a misunderstanding. Sorry for that. But if you are interested in the role of the resistors only as far as dc behaviour is concerned (stiffness of the base potential, temp. stabilisation due to dc feedback) I refer to my answer given below. –  LvW Aug 11 at 19:55

R2 is not effectively in parallel with RE. It is uncoupled to the extent of the hFE of the transistor.

Sure changes in current flow in the emitter are a direct result of current flow in the base. But the idea being described is to make the base resistors be an order of magnitude lower in size than the effective RE reflected back to the base.

Said another way the current that flows through R1 and R2 wants to be an order of magnitude bigger than the expected base current. This is so that the base bias voltage point does not shift around too much.

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It is the task of the emitter resistor Re to allow current-controlled voltage feedback. However, this works only in case the dc voltage at "other side" of the B-E path is kept constant (indpendent on temperature changes, tolerances and other uncertainties).

That means that a "stiff" base potential is desired. This would require a very low-resistive voltage divider. However, due to power consumption aspects and to ensure an acceptable input impedance (not too low), we arrive at a trade-off which results in the mentioned "rule of thumbs": Current through the resistors approximately 10 times the base current.

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First let me lead with a redrawn partial version of your circuit, which might be sufficient to convey the idea:

schematic

simulate this circuit – Schematic created using CircuitLab

Maybe that makes it easier to think about R1 and R2 in parallel. If not, read on...

Forget the transistor for now, and consider just a basic voltage divider, connected to some load:

schematic

simulate this circuit

Let's say that we want Vout = Vin/2, so we pick R1 and R2 to each be 1kΩ. What if RL is 250Ω?

R2 and RL in parallel are effectively:

$$ R_2 || R_L = \frac{1}{1/1\mathrm k\Omega + 1/250\Omega} = 200\Omega $$

Thus the actual behavior we get out of the voltage divider is:

$$ V_{out} = \frac{R_2||R_L}{R_1 + R_2||R_L} V_{in} = \frac{200\Omega}{1\mathrm k\Omega + 200\Omega} V_{in} = \frac{V_{in}}{6} $$

This is not the \$V_{out} = V_{in}/2\$ that we wanted. It can be shown that what we actually got was equivalent to the voltage divider we wanted (\$V_{out} = V_{in}/2\$), in series with the Thévenin equivalent of the voltage divider (which is R1||R2), into the load:

schematic

simulate this circuit

Here we see that this is just another voltage divider, but without any load. See, we get the same result:

$$ V_{out} = \frac{V_{in}}{2} \frac{250\Omega}{250\Omega + 500\Omega} = \frac{V_{in}}{2} \frac{1}{3} = \frac{V_{in}}{6} $$

Thus the rule of thumb for voltage dividers:

To make the error due to the load negligible, make the Thévenin equivalent resistance of the voltage divider at least 10 times smaller than the load.

When this rule is followed, then the current in the load is at least 10 times smaller than the current in the voltage divider, so the error introduced will be negligible.

Now, your transistor example is the same, but the current in RE is made smaller by a factor of \$h_{FE}\$. So, RL is equivalent to \$R_E \cdot h_{FE}\$. Otherwise we are just following the rule of thumb above about voltage dividers.

You can't ignore R1 because all the current through R2 or into the base must also go through R1. If you make either RE or R2 smaller, more current must flow through R1, thus there must be more voltage across R1, which might mess up your voltage divider if the change is large enough. The trick is to make the change in current due to variations of RE insignificant in comparison to the current already going through R1.

You could view R2 in parallel with your effective RL as the load for R1, and calculate your voltage divider based on that, but due to expected wide variations in \$h_{FE}\$, RL could in practice vary a lot. Thus, you want to design the circuit to be very insensitive to such variations.

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It is straightforward* to write the bias equation for this circuit using KVL as so:

$$I_C = \frac{V_{BB} - V_{BE}}{\frac{R_1||R_2}{\beta} + \frac{R_E}{\alpha}} \approx \frac{V_{BB} - V_{BE}}{\frac{R_1||R_2}{\beta} + R_E}$$

where

$$V_{BB}= V_{CC}\frac{R_2}{R_1 + R_2} $$

For bias stability, we want the right-most term in the denominator of the bias equation to be large relative to the left-most term which depends of \$\beta\$.

In other words, we want

$$R_E \ge 10\cdot \frac{R_1||R_2}{\beta} $$

or, rearranging,

$$R_1||R_2 \le \frac{\beta \cdot R_E}{10} $$

which corresponds to the requirement in step 3.


By writing the bias equation in this way, one can quantify (approximately) the improvement in bias stability against changes in transistor \$\beta\$.

For \$R_E = 0\$, the bias equation yields

$$I_C = \beta \frac{V_{BB} - V_{BE}}{R_1||R_2} $$

Thus

$$\frac{\partial I_C}{\partial \beta} = \frac{V_{BB} - V_{BE}}{R_1||R_2} $$

Now, let

$$R_E = x \cdot \frac{R_1||R_2}{\beta}$$

and find that

$$\frac{\partial I_C}{\partial \beta} = \frac{V_{BB} - V_{BE}}{R_1||R_2}\frac{1}{1 + 2x + x^2}$$

So, for example, doubling \$\beta\$ doubles \$I_C\$ for the \$R_E=0\$ case but, for \$x=10\$, \$I_C\$ increases by just a factor of \$\frac{2}{121}\$, about 1.7%

If, say, we wanted no more than a 1% increase in \$I_C\$ for a doubling of \$\beta\$, we solve the equation

$$1 + 2x + x^2 = 200$$

which yields

$$x \ge 13.2$$


*The Thevenin equivalent circuit connected to the base is:

$$V_{BB} = V_{th} = V_{CC}\frac{R_2}{R_1 + R_2}$$

$$R_{BB} = R_{th} = R_1||R_2$$

With this equivalent circuit, KVL around the base-emitter loop is:

$$V_{BB} = I_B\cdot R_{BB} + V_{BE} + I_E\cdot R_E = \frac{I_C}{\beta}\cdot R_{BB} + V_{BE} + \frac{I_C}{\alpha}\cdot R_E$$

Collecting terms and solving for \$I_C\$ yields

$$I_C =\frac{V_{BB} - V_{BE}}{\frac{R_{BB}}{\beta} + \frac{R_E}{\alpha}} $$

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@A.Centauri: If Vbb is the potential of the base versus ground I think we simply have Vbb=Vbe+Ie*Re. More than that, I don´t understand why the Thevenian equivalent here comes into play because we speak about dc voltage division at the base node and not about a source resistance. Am I wrong? –  LvW Aug 12 at 7:57
    
@LvW, \$V_B = V_{BB} - I_B\cdot R_{BB} \$ is the base voltage, not \$V_{BB}\$. \$V_{BB}\$ is the Thevenin voltage of the circuit connected to the base and, thus, is the voltage on the base when the base current is zero. See Marshall Leach's BJT bias equation notes: users.ece.gatech.edu/mleach/ece3050/notes/bjt/bjtbias.pdf –  Alfred Centauri Aug 12 at 10:45
    
@A. Centauri, OK - I see. The problem was that I didn´t know in your contribution the meaning of VBB. –  LvW Aug 12 at 11:09
    
@LvW, I've clarified that section. –  Alfred Centauri Aug 12 at 11:14
    
@A.Centauri-just for your information: Using "my" design approach requiring I(R2)>10*IB we arrive at a similar design rule: R2<β⋅[RE/10+VBE/(10*IC)]. –  LvW Aug 12 at 12:15

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