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Sorry if this is an obvious question, I come from a software background and don't know the names for a lot of components. I am designing some custom hardware based around a W65C02S processor (a modern version of the classic MOS 6502). This processor (data sheet here) has only a 16 bit parallel bus for talking to other chips but to interface with modern peripherals I need GPIO functionality. Are there any ICs which would provide setting/reading a GPIO line state by communicating with the parallel pins on this chip?

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Is this 16-bit "parallel bus" truly GPIO, or is it a memory-mapped interface bus? – MarkU Aug 16 '14 at 4:44
it is a memory mapped interface – S E Aug 16 '14 at 4:48
Just stick a 74'573 at the end. – Ignacio Vazquez-Abrams Aug 16 '14 at 5:23
I think he's suggesting a commonly available 74HC573 or 74HCT573 octal latch to capture the data bus D0-D7. I'm not sure which timing signal you need to capture on, the 32-page data sheet is a bit thin for a microcontroller... no timing diagrams... you will also need an address decoder gated by one of the clock timing outputs. I'm not finding timing info on the westerndesigncenter website though, may have to fall back on the old 6502.org website. – MarkU Aug 16 '14 at 5:49
Data read/write timing setup and hold are relative to the Phase 2 falling edge. Old data sheet link: archive.6502.org/datasheets/mos_65ce02_mpu.pdf – MarkU Aug 16 '14 at 5:52
up vote 9 down vote accepted

The W65C21 PIA (Parallel Interface Adapter), also made by Western Design Center (WDC) along with the W65C02S, is a parallel GPIO chip specifically designed to work with the address/data/clock interface of the 65xx series of chips. (The 6521 is patterned after the 6821 PIA that was designed by Motorola to go with the 6800 microprocessor).

You may also see references to the 6520 and 6820; the entire family of 6820, 6821, 6520 and 6521 PIA's are all pin compatible and were designed by Bill Mensch, the founder of WDC. Mensch also was instrumental in the design of the original 6800 and 6502.

The 6521 has two 8-bit bi-directional I/O ports, automatic handshake control of data transfers, and two interrupt line outputs.

enter image description here

By adding some decoding to the address lines, creating individual chip selects, you can put as many 6521's on your system as needed.

The 6521 was the preferred way to add parallel ports to a 6502 processor 35 years ago, and still is. Although the Apple ][ didn't have any on its main board, some of the I/O boards used it, such as the one below (it used a Motorola 6821 instead of the 6521, same functionality as mentioned earlier). The Apple 1 had a 6820 on its main board. The Commodore PET had two 6520's on its main board (used for the keyboard).

enter image description here

The W65C21 is available at Mouser in various packages.

You might also want to check out the W65C22 VIA (Versatile Interface Adapter), which is like the 6521 (two parallel ports) but in addition has two 16-bit timers and a shift register. The 6522 was also used on the main board of the PET. The W65C22 is available at Mouser.

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Excellent answer (so +1 from me) but I seem to remember it was the 6522 VIA used in the Pets – JIm Dearden Aug 16 '14 at 11:52
@JImDearden The PET had two 6520 PIA's (functionally the same as a 6521) and a 6522 VIA. The VIA had two parallel ports like the 6521 plus two timers and a shift register. As shown on page 1 of the PET schematic. – tcrosley Aug 16 '14 at 15:26

One possible solution would be to convert the parallel bus to I2C, and then use any number of I2C to GPIO chips.

Perhaps some combination of:

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this should be fun I just have to bitbang SPI and some other custom protocols over I2C over parallel – S E Aug 16 '14 at 4:45
This is a terrible answer. How are you going to bit-bang anything if you don't have any GPIO pins to begin with?!? – Dave Tweed Aug 16 '14 at 11:30
the parallel to spi chip provides the interface to a gpio enumerator. its a messy solution, but it would work. At the time there was no better answer – S E Aug 19 '14 at 8:11

Implement a memory bus interface and any peripherals you need (GPIO's, UART's, SPI, I2C, anything at all really) in an FPGA.

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Or just put the soft core in the FPGA instead and save a chip. – Ignacio Vazquez-Abrams Aug 16 '14 at 17:05

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