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I am using 74LS154 4 to 16 decoder Link to *.pdf here. It has two ACTIVE LOW 'ENABLE' pins at the input. What is the use of two ENABLE input pins is the question.

Most of the 74 series IC's used in the lab has two ENABLE pins..

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My hunch is that one enable used to be driven from an address decoder (so a microprocessor could address several pieces of hardware) and the other from output enable. –  jippie Aug 23 at 9:17
    
Both the ENABLE pins are tide to an AND gate. –  turtle Aug 23 at 9:38
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I suppose one pin could have been left as a no-connect/do-nothing pin but why do this when there are probably a few applications that can make use of the dual enable pins. –  Andy aka Aug 23 at 10:08

3 Answers 3

It's just simply to reduce the "glue logic" needed in implementing the device. It's simple enough to simply just tie the one input to low to just the pin as a single input but tis gives more flexibility in implementation.

If you look at the package you realize that without the extra /enable that package would have an NC pin. I suspect the first designers decided that having a little extra functionality for "free" (i.e. in pin count) would be an enhancement.

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The ENABLE pins were active LOW and tide to the AND gate, its as good as applying one LOW input.So I could not think of any use and was wondering if there could be any other reason other than uing up a no-connect pin. Thanks to all and it looks like using up the NC pin was the option. –  turtle Aug 25 at 16:49

That's interesting that they would have two active-low enable pins and no active-high enable pins. I'm not entirely sure what you would need that for. I suppose it acts like a free AND or OR gate on the enable input, depending on how you want to look at it, which could be uselful in some applications. However, the 3 to 8 line decoders generally have 3 enable lines - one active-high and two active-low. You can use the active high pin on one chip and the active low pin on another chip to cascade two 3-to-8 decoders into a 4-to-16 decoder as the 4th input line drives the complementary enable lines.

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The enable pins are ANDed so you can make a 32-output decoder with two inverters and four decoder chips. Arguably it might be more useful in smaller systems if one of the inputs was inverted, but imagine they had a meeting on some Monday in 1965 or whatever and, over coffee and maybe cigarettes, decided to make an it a symmetric enable input.

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