Take the 2-minute tour ×
Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It's 100% free, no registration required.

Title pretty much says it all. But how do most IC's, micro-controllers, etc. know when a clock cycle starts a downward or upward transition from the clock source?

share|improve this question
I have a mental exercise for you: If you have an image of a square wave, how would you find the rising and falling edges? What mental process are you using to pin point them? Try to describe in detail how you manage to find them. –  jippie Aug 23 '14 at 15:42
Stating the question in terms of knowledge always makes me worry that the interlocutor might be over-personifying things. On the off chance that this is going on, let me say again that the chip doesn't need to "know" it just has to be designed to to function in certain ways when that happens. The answer so far have explained how to accomplish that. –  dmckee Aug 23 '14 at 21:43

2 Answers 2

up vote 6 down vote accepted

By comparing the signal in two points of time.

Given that real gates have a non-zero propagation time, this shows a simplification of such:


simulate this circuit – Schematic created using CircuitLab

At rest state, IN is low and hence the inverter output is high. This results in a low at OUT. When IN switches to high, the high reaches both the inverter and and gate within picoseconds of each other. The inverter is still outputting high at this time, so the and gate switches to outputting high. The propagation time of the inverter then elapses and its output switches low. This propagates to the and gate, which then switches low. This low-high-low transition at OUT indicates that we have detected a leading edge.

share|improve this answer
Ah, that's a nice explanation. On a side note, I could see that kind of circuit causing issues in high-frequency applications? Ignoring propagation delays and the speed of electricity, that bounce would never happen. Obviously, in real-life it does. But that makes sense. –  cbmeeks Aug 26 '14 at 13:38

In general they don't "know" when the clock line starts a transition- the effect takes place somewhere in the middle between valid 1 and 0 states.

The simplest circuit that starts with gates and illustrates the effect of a clock edge (rather than a level) is probably the master-slave flip-flop. The diagram below is taken from here, and I would have shown the input clock as inverted (because it is a negative-edge-triggered JK flip-flop).


It consists of two RS (level triggered) latches with some gates.

The master is locked out from changes at the instant the clock goes low, and the current state of the master is passed to the slave, also at the falling edge of the clock. So you can consider the J and K inputs as having been 'sampled' at the falling clock edge. If given states on the J and K inputs are present slightly before the clock edge (setup time) and slightly afterwards (hold time) they will define the output state once the clock has reached low level and things have settled out.

Note that the clock edge is required to transition the "no mans' land" between 1 and 0 fairly rapidly when the outputs Q and /Q are part of the logic equation for J and K since they must not change during the clock transition (and should stay valid for a short time). What buys you this time is the propagation delay of the gates. This is the reason for maximum clock rise/fall time specifications- fast gates require sharper clock signals. If the input clock is not guaranteed to be a nice sharp waveform, a Schmitt trigger or just a lot of gain can clean it up.

share|improve this answer
@PhilFrost Yes, maximum rise/fall time, minimum slew rate. Thanks, will edit. –  Spehro Pefhany Aug 23 '14 at 20:35
When using a master/slave arrangement, I would think one could cheaply and easily improve noise tolerance by saying that the master master latch will only capture its input while the clock input is significantly above mid-rail, and the slave will capture its input (the master's output) when the clock input is significantly below mid-rail. I don't think I've seen that done much, but it would seem like it would allow one to eliminate all race conditions provided the clock doesn't rise or fall too fast (which could be ensured by using a simple RC delay). Such a design would be a bit different... –  supercat Aug 23 '14 at 21:40
...from a Schmidt trigger (if the clock is noisy, the input would need to be stable any time it was near the master-latch threshold, and output may not switch cleanly until the clock is cleanly past the slave-switch threshold, but if all devices run from a common clock, the outputs would be clean whenever anyone cared about them, even if the clock was noisy. Any idea if such approaches are used much these days? –  supercat Aug 23 '14 at 21:43

Your Answer


By posting your answer, you agree to the privacy policy and terms of service.

Not the answer you're looking for? Browse other questions tagged or ask your own question.