Title pretty much says it all. But how do most IC's, micro-controllers, etc. know when a clock cycle starts a downward or upward transition from the clock source?
By comparing the signal in two points of time.
Given that real gates have a non-zero propagation time, this shows a simplification of such:
At rest state, IN is low and hence the inverter output is high. This results in a low at OUT. When IN switches to high, the high reaches both the inverter and and gate within picoseconds of each other. The inverter is still outputting high at this time, so the and gate switches to outputting high. The propagation time of the inverter then elapses and its output switches low. This propagates to the and gate, which then switches low. This low-high-low transition at OUT indicates that we have detected a leading edge.
In general they don't "know" when the clock line starts a transition- the effect takes place somewhere in the middle between valid 1 and 0 states.
The simplest circuit that starts with gates and illustrates the effect of a clock edge (rather than a level) is probably the master-slave flip-flop. The diagram below is taken from here, and I would have shown the input clock as inverted (because it is a negative-edge-triggered JK flip-flop).
It consists of two RS (level triggered) latches with some gates.
The master is locked out from changes at the instant the clock goes low, and the current state of the master is passed to the slave, also at the falling edge of the clock. So you can consider the J and K inputs as having been 'sampled' at the falling clock edge. If given states on the J and K inputs are present slightly before the clock edge (setup time) and slightly afterwards (hold time) they will define the output state once the clock has reached low level and things have settled out.
Note that the clock edge is required to transition the "no mans' land" between 1 and 0 fairly rapidly when the outputs Q and /Q are part of the logic equation for J and K since they must not change during the clock transition (and should stay valid for a short time). What buys you this time is the propagation delay of the gates. This is the reason for maximum clock rise/fall time specifications- fast gates require sharper clock signals. If the input clock is not guaranteed to be a nice sharp waveform, a Schmitt trigger or just a lot of gain can clean it up.