Designing a 4-bit ALU to compute various functions

Question

I've been working on designing an ALU that calculates various functions but I don't really know how to separate each function from one another. The inputs are 4-bit numbers A and B. I have a decoder that selects which function to use, but I don't know how to implement the functions from the decoder. The ALU needs to do arithmetic operations and also logical operations. If anyone knows how to go about structuring an ALU that has 2 4-bit inputs and 1 4-bit output, any guidance would be appreciated. Thanks.

Answer 1

In terms of "separating" the functions, that's not really how digital logic works. Digital logic is "always doing everything". You need a mux (multiplexer) in there. The multiplexer is used to pick the right output from all of those generated.

Assume inputs A and B, output Q. Assume the ALU does two different things: Q=A+B, or Q=A&B.

The ALU will have an adder. It will also have a big AND gate.

A and B both go to the adder, and the AND gate. Always. Every moment of every day, the adder is adding A and B, and the gate is ANDing A and B.

The mux is used to select which one of the outputs we want to pass to Q. If the control signals to the ALU say "add", then the mux will select the output of the adder and pass it to Q; the output of the AND gate is unused. If the control says "and", the mux will select the output of the AND gate and pass it to Q instead, while the output of the adder is unused.

Imagine A = 0b0001 and B = 0b0010 on the inputs of the ALU. The adder is always producing 0b0011, and the AND gate is always producing 0b0000. If you provide the "add" control signal, the 0b0011 is passed to Q. You can leave A and B alone, and change the control signal to "and", then 0b0000 is passed to Q.

Answer 2

Perfect ALU design articles are here : http://www.6502.org/users/dieter/

Answer 3

Here is an example of a 2-bit ALU. As you can see XOR, and, or are computer by the first 3 logic gates. Then two XOR gate are used to determine the sum value. Then two AND and an OR gate are used to determine the carry on value. You can work out the truth table and see that it works. The carry is then fed to the logic for the second bit which works the same way. The decoder then selects the operation. You just have to continue the same pattern and extend it to 4 bits.

For adding three bits (C is the carry over) the truth table is:

A B C  (A+B) Carry
0 0 0    0     0
0 0 1    1     0
0 1 0    1     0
0 1 1    0     1
1 0 0    1     0
1 0 1    0     1
1 1 0    0     1
1 1 1    1     1

You can find out how to implement these two logic functions using a Karnaugh map

Answer 4

Here is a 4-bit ALU in VHDL. If actual hardware is required the code could be implemented in a suitable CPLD.

Answer 5

For a 4-bit word width a parallel ROM (EEPROM, Flash) is the easiest way to implement it. Use both input words, combined with the operation (probably also 4 or 5 bits) as the ROM's address, and it will output the result for that combination. If the operations include multiplication the output has to be eight bits wide, which any current parallel ROM will handle. If you have at most 32 operations you'll only need an 8K byte ROM (\$2^{2 \times 4 + 5} = 8192\$)
The most difficult task (and even that's not so hard) is to write a program to create the ROM's content.