Tell me more ×
Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It's 100% free, no registration required.

I have a testbench and a verilog modules. I want to write ouput of the testbench to a file anmed as output.txt. While doing this job, I want to use $monitor.

Is it possible ? If yes, can you give me pseudo code of that segment ?

share|improve this question

2 Answers

use $fmonitor:

integer f;
initial begin
  f = $fopen("output.txt");
  $fmonitor(f, "time=%5d, v=%h\n", $time, vv);
  #1000 
  $fclose(f);
  $finish;
end
share|improve this answer
up vote 2 down vote accepted

I have wrote Makefile to meet that desire ;

default :
iverilog -o verilog_testbench lab_work.v test_bench.v 
odt  :
./verilog_testbench > simulation.odt
txt  :
./verilog_testbench > simulation.txt

I have tried Taniwha 's answer before, but It did not work. So, I have wrote Makefile.

share|improve this answer

Your Answer

 
discard

By posting your answer, you agree to the privacy policy and terms of service.

Not the answer you're looking for? Browse other questions tagged or ask your own question.