While looking through some Verilog code, I came across this:
input [7:0] data [0:16]
The code referred to this as memory.
Could someone explain what it does? I have only dealt with single dimensional arrays before (only one [])
I'm assuming it has something to do with SRAM, but as far as I know SRAM memory is allocated using altsyncram
So what does it do? Thank you.
This looks like a 2 dimensional input port and not a RAM. I presume this is systemverilog, as verilog does not support 2d ports. This behaves like 17 8-bit ports, data[0], data[1], data[2], etc. up to data[16]. Individual bits would be data[0][0], data[0][1], etc. Basically this is an organized way of providing 17 data ports, each with 8 bits. In regular verilog, you would have to either provide 17 separate inputs or you would have to provide one 136 bit wide input.
Decent synthesizers can infer block RAM from 2d arrays in many cases - altsyncram is not the only way to get a RAM. If you want to write FPGA vendor independent code, then you can't use altsyncram and instead have to write verilog that will cause the synthesizer to infer RAMs. I know Xilinx has a user manual for the synthesizer that explains how to do this (XST user guide); I presume Altera would have something similar.
