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I'm trying to build a framebuffer using an FPGA and an external memory. I have a soft core CPU running on the FPGA as well a small chunk of logic to output signals to an LCD. My goal is to have the CPU rendering/writing a frame to a small chunk of external memory and then have the LCD write module read from that external memory.

My issue is that the LCD and write code is on a crystal-->PLL at 9Mhz and the CPU is on the original crystal at 50Mhz. Do I have to put the CPU on the PLL as well or is there a way of interfacing the logic in such a way that it will work as is?

Specs:

Memory => SDRAM @ ???Mhz

CPU => NIOS II @ 50Mhz

LCD => Sharp 480x272 @ 9Mhz

FPGA => Cyclone III

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2 Answers 2

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You'd have to set up synchronization registers across the clock boundaries. And as the clocks are out of phase with each others, there's always the possibility of metastability, but I suppose the FPGAs are not very susceptible to metastability.

I would suggest to run your CPU at some "easy" multiple of 9 MHz, perhaps 9 x 4 = 36 MHz or 9 x 8 = 72 Mhz and divide the 9 MHz clock to the LCD from there. It would be much easier and reliable. The clocks would be phase aligned with each other; no possibility of metastability, ever, and normal synchronous design rules could be used. I'd suggest that you consider it.

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I would recommend using an asynchronous FIFO for the synchronization. Write a module that runs at 9 MHz and draws data from the FIFO to output to the display. You may need to send a few sideband signals through the FIFO as well as the data so the interface code knows where the frame and the rows start. Then write another piece of code that will read the frame data out of memory and write it to the FIFO, pausing when the FIFO is full. This code would run in the same clock domain as the main CPU to eliminate any synchronization issues between the two.

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  • \$\begingroup\$ This is really the best solution. You should fill the FIFO with burst read transfers from the SDRAM. \$\endgroup\$
    – Grabul
    Nov 15, 2014 at 20:15
  • \$\begingroup\$ This might be the most flexible and efficient solution, but to get the project started and things rolling, keeping synchoronous clocks is usually the easiest solution. \$\endgroup\$
    – PkP
    Nov 16, 2014 at 3:37
  • \$\begingroup\$ Well, using a FIFO might be a good idea even if both ends are in the same clock domain. Using a FIFO would loosen up the timing requirements for memory reads, just in case there is a conflict with the CPU. It also allows for efficient utilization of bust accesses, presuming the memory supports burst reads. \$\endgroup\$
    – alex.forencich
    Nov 16, 2014 at 9:11

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