Xilinx System Generator: A summary of frequent errors during the Simulink - modelling stage

Question

I wonder if there is a kind of guide or summary about tipical errors at modelling design stage that users tend to do.

Thank you so much for your help.

By the way. Some people ask me why I don´t use the official site to ask these kinds of questions. Besides I do, the reason I use this site is because is faster in getting answers to me than the official site of Xilinx

Answer 1

There is a good reference guide of errors for every xilinx program in this link: http://www.xilinx.com/support/answers/

I can find the description of the error for a particular xilinx program and the solution.