Your signals look to be buried "within" a ground pour. This will affect propagation delays compared to if they are just running over a reference plane. Do you have a solid plane on the adjacent layer? Were the calculations of acceptable mismatch done with this in mind?
Actually, do you really need to match that accurately? Is this some spec handed down from on high by a silicon vendor?
50mils is a tiny difference in terms of time-of-flight. I'm a metric-head, 40mils is ~1mm. signals travel at ~60% of speed of light. 1mm is single-digit pico-seconds!
I've personally designed board with 125MHz DDR RAM with much less tight matching than that and had plenty of margin when I tested.
Get a copy of Black Magic for lots of practical advice on this sort of issue. Also read the si-list.
Regarding 90 degree bends, there's a fair bit of evidence that at sub-10GHz the signals don't actually see them. For example (from si-list) this thread:
There's a lot more to it than just "matching lengths", as actually what needs to be done is to match "flight-time", which is a whole bigger ball game.