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Say there are 2 Shift Registers chained together with the following values

SR1 : 11111111
SR2 : 11001111

The data is written to SR1 and then to SR2 like:

digitalWrite(SensLatchPin, LOW);
shiftOut(SR,LSBFIRST,B11001111);//SR2
shiftOut(SR,LSBFIRST,B11111111);//SR1
digitalWrite(SensLatchPin, HIGH);

If the SR2's data is changed with time, does SR1 refresh (as in, set all outputs to 0 and then reset to the same value)?

For example, the following code is executed (only change for SR2)

digitalWrite(SensLatchPin, LOW);
shiftOut(SR,LSBFIRST,B11101111);//SR2
shiftOut(SR,LSBFIRST,B11111111);//SR1
digitalWrite(SensLatchPin, HIGH);

In the above case, does the SR1 outputs toggle or does it remain same without any transition (as the values before and after latching are same?)

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  • \$\begingroup\$ I would expect not, but it depends on the library code and maybe on how the SRs are connected. \$\endgroup\$
    – Wouter van Ooijen
    Apr 8, 2015 at 6:23
  • \$\begingroup\$ @WoutervanOoijen The SR's are connected in a typical way i.e. Out of SR1 feeds into Data of SR2. I don't see how library code will affect this as the Latch is controlled by user. So it drills down that is a Shift Register sees same data and lacthes again, then does the output refreshes!? \$\endgroup\$
    – Anuj Purohit
    Apr 8, 2015 at 6:32
  • \$\begingroup\$ Surely this is simple enough to test using your own circuit, code and choice of components. What does your scope tell you? \$\endgroup\$
    – Roger Rowland
    Apr 8, 2015 at 6:34
  • \$\begingroup\$ @RogerRowland Scope is shared between people ( :( ) so I will have to wait for some time to see it. \$\endgroup\$
    – Anuj Purohit
    Apr 8, 2015 at 6:35

1 Answer 1

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Your question text contradicts itself a bit:

"2 Shift Registers chained together"

does not match with

"data is written to SR1 and then to SR2 "

From your comment I understand that the SRs are chained, SR1 directly to the uC, SR2 to SR1.

In that case each shiftOut call transfers its data to SR1, and simultaneously trasnfers the content of SR1 to SR2.

Assuming that you use SRs with separate shift and hold registers, the output should not glitch when you 're-issue' the same value for a pin, but do check the datasheet of you chip. Very short glitches around a clock edge are always a possibility, and most datasheets do not completely rule this out.

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  • \$\begingroup\$ Your understanding " I understand that the SRs are chained, SR1 directly to the uC, SR2 to SR1." is correct. I am using TI 74HC595 but cannot find this detail in the data sheet. It is a obvious mention or do I need to deduce it? \$\endgroup\$
    – Anuj Purohit
    Apr 8, 2015 at 7:28
  • \$\begingroup\$ @AnujPurohit: This data sheet shows everything very clearly. \$\endgroup\$
    – EM Fields
    Apr 8, 2015 at 12:49
  • \$\begingroup\$ Sorry.. Cannot get the point \$\endgroup\$
    – Anuj Purohit
    Apr 8, 2015 at 14:11
  • \$\begingroup\$ @EM Fields: I am not so sure. There is a specification of Tpd RCLK->Q* (delay from register clock to output) of some 10's of ns. But there is no explicit guarantee that there is only a single transition in this period, which is what Anuj is asking about. \$\endgroup\$
    – Wouter van Ooijen
    Apr 8, 2015 at 15:43
  • \$\begingroup\$ @WoutervanOoijen: The cells in the shifter and the output latch all seem to be clocked RS latches, so the possibility of glitches in the outputs of the chip seems to be vanishingly small, especially since the 595 is a mature work of art and no problems of that type are reported on the data sheet. But, I don't really know what he's going on about, so my guess could be wrong. \$\endgroup\$
    – EM Fields
    Apr 8, 2015 at 18:04

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