VHDL: Instantation question

Question

I have to do a instantation of several components

I suppose the code for this instantation would be something like this:

componentA: componentB port map(
output_ca => input_cb
); 
componentA: componentC port map(
output_ca => input_cc
); 

But I know that part of the code before is wrong, because 'ouput_ca' has 6 bits and input_cb, and input_cc has only 3 bits every one of them. How would be written this code in a good way? Thank you so much for your help.

Answer 1

You must use some signals, you can't map straight from one pin to another (I'm also using direct instantiation to avoid creating component declarations - see also my answer here):

signal aout : std_logic_vector(5 downto 0);

A: entity work.componentA port map(
    output_pin => aout
); 
B: entity work.componentB port map(
    input_pin => aout(5 downto 3)
); 
C: entity work.componentC port map(
    input_pin => aout(2 downto 0)
); 

---

Aside

You seem to be confused in your instantiation syntax. You wrote:

componentA:componentB port map (...

implying that componentA connects to component B.

What is actually being said is

individual_name_of_component: name_of_entity

So you pick an entity which you are instantiating on the right of the : and give it a name on the left.