Honestly, if you really want a netlist format that will in practice work with just about any tool, you have just two serious choices:
Yes, these are full-blown hardware description languages, and using them as a netlist format could be considered overkill. However, it is very easy, and if a tool spits out simple, structural VHDL or Verilog, you can be quite confident that you'll be able to pull the design back into just about any other EDA tool.
As a side benefit, most other netlist formats (e.g. EDIF) need to have an externally defined set of primitives -- either something vendor specific, or something like LPM. With VHDL and Verilog, the lowest level leaves (primitives) can just be whatever you want (e.g. synthesizable RTL code, simulation models, black boxes, etc).
However, if you absolutely must have an actual netlist format, I second the suggestion to use the gnetlist format, which can then be converted to many other formats.