We're looking into modeling and checking a simple mesh fabric coherency protocol for checking RTL simulation. In the past, we've completely rolled our own solution for listening to packets in the RTL and then generating an expected response or multiple possible expected responses.
e.g. for a flow like this:
Core Memory Controller
| |
| Request $Line in E-state |
+------------------------->|
| |
| Data |
<--------------------------|
| |
The checker on the Memory Controller needs to predict that the Data packet will be returned to the Core and what the payload of that packet would be.
What are the available frameworks for modeling these flows? I'm aware of TLM and am looking into it. Are there any others? I'm open to any language. Are there any formal verification protocol tools that can also generate checkers or assertions?