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I have posed a question, "Function run in MCU generate noise to the analog circuit", before but at that time the question was not detailed enough. After several days` of testing, the problem is now more specific.

When I run a function with 600 Hz frequency, I can observe a set of noise (600 Hz, 1200 Hz, 1800 Hz, etc.). Here is the frequency spectrum:

Enter image description here

After some tests, I think it is due to the improper decoupling of the VDD of the microcontroller. But I am not sure. I did another test. I found that when the capacitors (inside red circles) changes their value from 0.1 µF to 0.01 µF, the noise decreases.

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And the noise after the change:

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My question is:

Why would the noise decrease after the change? Is it due to the improper decoupling of the microcontroller? (but 0.1 µF is recommended in the STM32F4 datasheet).

Here is the PCB of those pins and capacitors:

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    \$\begingroup\$ You labels on the schematics seem to be DGND and on the pcb prints AGND which makes me wonder if you actually seperated both grounds or if your digital return current runs through the analogue ground. It might be useful to have a full picture of the routing of all layers. \$\endgroup\$
    – PlasmaHH
    May 29, 2015 at 14:40
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    \$\begingroup\$ It's not unusual to have a mix of bypass capacitors for this reason: have a 0.1uF AND a 0.01uF. The ESR of the 0.1uF caps may be too high. \$\endgroup\$
    – pjc50
    May 29, 2015 at 14:42
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    \$\begingroup\$ The larger capacitors may be coupling more noise into the analog circuit- so improving the digital supply at the expense of the analog. You could test this hypothesis vs. the lower-Z hypothesis by paralleling a lower value cap with the higher value (just stack them) rather than changing the capacitors. \$\endgroup\$ May 29, 2015 at 14:57
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    \$\begingroup\$ Does it make sense that a .01uF or .1uF cap should make much of a difference at 600Hz? I guess I'm leaning towards Spehro's explanation, that the coupling is getting worse and therefore transferring less noise from the digital circuits to AGND. \$\endgroup\$
    – scld
    May 29, 2015 at 15:31
  • \$\begingroup\$ Could you provide a link to your old question? Also, are there buried power and ground planes in this design or are the power and ground routed on tracks (I think I see tracks)? \$\endgroup\$
    – The Photon
    May 29, 2015 at 15:39

2 Answers 2

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As pointed out in the comments:

If you have connected the digital and analogue grounds all over your PCB, the digital return current will happily mix with the analogue return current and couple into it, those spikes will then have a much bigger influence in your measurements. Of course if the analogue path is also (partly) inside the MCU, you might have to mix a little here and there, but you could still try to limit the AGND and DGND overlap.

The second thing is, the peaks reduce, because a 100nF capacitor will have a larger equivalent series resistance, it will take some more time to get the charge from it's more complex/longer plates out into your chip. The smaller value has a lower ESR, which will supply the power back to the MCU much quicker, making the peaks much smaller. If you put a 100nF and 10nF, or even 4.7nF next to each other on each VDD pin you will reduce the coupled noise in the case of fast internal switching and of more powerful but more slow external switching much better than with just either of them.

In some cases even 3 or 4 different values are used to cover all the frequency domains, though usually we are talking about single MHz, 100's of MHz and (near) GHz domains in a single chip, such as high end processors, WiFi or FPGAs when there's 4 different sized caps on the power pins.

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  • \$\begingroup\$ Thank you for your answer. But I have designed similar PCBs before. Each time I did not separate the digital ground and analogue ground. But I have not seen such phenomenon in my question before. So is it very necessary to separate the ground? \$\endgroup\$
    – billyzhao
    May 30, 2015 at 9:35
  • \$\begingroup\$ Necessary? No. Very smart to do so if you can: Yes! The point is, all the digital current will go through your analogue return paths as well and it will "lift" up the analogue ground voltage at each peak. If the digital and analogue power can only return to the power source separately they cannot interfere with each other. \$\endgroup\$
    – Asmyldof
    May 30, 2015 at 9:44
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The +3.3 V connection should go to the capacitor, which should then be connected directly to the MCU lead, in every case, as you have it with C302. It shouldn't be between the capacitor and the lead.

That diagonal track in the third image should connect to the lead at a right angle. That won't affect the decoupling but it can act as an acid trap when etching. It also looks ugly.

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  • \$\begingroup\$ Thank you. I wonder what should be the right angle? Could you explain a little? \$\endgroup\$
    – billyzhao
    May 30, 2015 at 9:38
  • \$\begingroup\$ You just need to avoid an acute angle. A 90 degree (a right angle) or a straight connection to the pad or another track are advisable. \$\endgroup\$ May 30, 2015 at 9:50

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