# Design 3-bit Synchronous Counter

I'm new to the whole electronic circuit scene, I've been trying to work out for hours how to design a 3-bit synchronous counter using D-Flip Flops to count in a given sequence.

So say for instances that the counters sequence is 111->010->011->001, what is the best approach to this problem?

any help much appreciated.

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You can create a 3-input, 3-output circuit that maps one state in the count sequence to the next. Then feed the 3 Q outputs of the FF's into this combinatorial circuit, and connect the output of the combinatorial circuit to the 3 D inputs of the FF's. Connect all 3 of the FF's clock lines together, and then whenever an active edge comes along the flip flops act like a 3 bit register, and just load up the next value.

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The official way that you'll get taught in school is to learn Karnaugh Maps, and use one per to work out the logic to compute the next value of each bit. Then you work out what set of gates will implement said logic and wire it all up.

I won't bother telling you that one. I'll tell you two ways a hardware hacker does it: the easy way and the clever way.

# The Easy Way

Get three one-of-eight multiplexer (MUX) chips, such as the TI SN74LS151. This chip uses three lines (A, B, C) to choose one of eight inputs (D0 through D7) to route to its output (Y).

Connect the three D flip-flop (DFF) outputs to the three select pins of each chip, with the least-significant bit going to A and the most-significant bit going to C. Connect the Y output from each MUX to the D input of its respective DFF.

The W pin is an inverted version of Y; you don't need it so don't connect it. The G pin is an active low enable; connect it to logic 0 (GND).

At this point, all you have to do is wire each D pin on each multiplexer to VCC or GND to set the next state for the DFFs, where the D input number is the current state. For your example (111->010->011->001), the first state is 7, and it advances to 2, so the D7 pins on the bit 2 and bit 0 MUXes are tied to GND, and the bit 1 MUX is tied to VCC. The next state is 3, so the D2 pins on the bit 0 and 1 MUXes are teid to VCC and the one on bit 2's MUX is tied to GND.

Any unused D pins on the MUXes need to be tied to some level; in this case, I'd recommend tying them all to VCC since your first state is 111.

The great thing about this circuit is that you can completely change the count order just by rewiring the D pins. Also, this is how modern FPGAs implement combinational logic, with what are effectively lookup tables.

# The Clever Way

You can get one more input bit to your function by realizing that you could connect the D pins to Q or Q-bar from the LSB DFF, and not just VCC or GND. In your example, you could use a dual 4-to-1 multiplexer such as the SN74LS153, and eliminate a MUX chip (one of them can handle two DFF inputs).

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For each bit, identify which of the eight states should cause it to be "1" in the next state, and which ones should cause it to be zero. Then write a function which is high or low for the appropriate combination of inputs.

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