Fanout is how many inputs a gate output drives. I think knowing the average fanout can give you an idea of how efficiently routed or congested your design may be, and probably how likely to meet your timing constraints. Usually there will be a full report that will also tell you about the nets with high fanout (may report the top 10, or how ever many you ask it to), and logic with maximum delay.
The non-global routes used for normal routing have a much higher delay than global routes (usually used for clock and high fanout nets e.g. reset) so the maximum clock speed will suffer if these nets are very large.
There is usually a setting to limit how large the fanout of a net can be before it gets automatically promoted to a global net, often set to say less than 50. The router will try to automatically duplicate the gate driving the net (or insert a buffer if this is not possible) to avoid exceeding this limit. However if the design is very congested this may not be possible, so a review of the floorplanning or HDL may be in order.
On a related note, it is very important to know about the types of reset your logic can handle. Using the wrong reset or just using reset at all with some blocks, can easily turn a very small design into a large one.
There is a lot more to this can be written about easily here. I would pick up a good book on FPGAs, and/or read the app notes for your FPGA manufacturer who will certainly have plenty written on this subject and more.