VHDL type mismatch error

This is my first question.

I have a package that contains the following type:

type t_rgb_64x48 is array(0 to 47) of std_logic_vector(63 downto 0);


and is being used in my file.vhd file.

file.vhd contains an entity that contains the type of the package mentioned earlier:

RData_in : in t_rgb_64x48;


It also contains a signal with its corresponding type:

type t_vgaram is array(0 to 479) of std_logic_vector(639 downto 0);
signal s_rstorage : t_vgaram;


I need to access s_rstorage through the following statement:

s_rstorage(ColumnAddress_End downto ColumnAddress_Start)


to store the value of RData_in to s_rstorage and making sure that they are of the same width in 2D.

The problem is this error:

Type of s_rstorage is incompatible with type of RData_in.

I know that they have different types as the cause of the error. But how do I fix this problem?

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