Cyclical output counts from a D Flip Flop, what is this effect called?

Question

While working on a frequency divider/counter (in this case a frequency subtractor) using flip-flops, I discovered a strange effect in a D flip-flop when I left the clock at a constant frequency, but varied the frequency of the D input.

In this LTSpice sim, the CLK is at a constant 2.88MHz, and the D frequency is stepped through from a range of 0.1MHz to 7MHz

.

After exporting the output of Q and processing the data in Python, I counted the amount of rising edges that took place, with respect to the frequency of the D input.

The relationship looks like the following. X axis is frequency of D in MHz, Y axis is number of rising edges from Q in a 5ms window

First thing of note is that the minimum counts occur at multiples of 2.88MHz (The clock), but what I was surprised to see is that the shape remained the same in both the region where Freq(D) was less than Freq(CLK) as well as greater. Even more surprising is the fact that on a more fine-grained simulation, the results are effectively linear

I set out to create a frequency subtractor which I suppose it is in certain regions, but all-in-all I wouldn't know what effect this is called, or why it produces this output. I would appreciate any speculation or further reading on the uses of flip-flops in ways like this.

Answer 1

The effect is basically Aliasing.

Your clock makes a digital sampling system, whenever the data signal is less than half the clock your data signal will determine the number of edges in a window large enough to count them, when the data signal is larger than half the clock frequency they start to interfere in a pattern that is, when taken with sufficient samples, a triangle waveform in the way you plot the data.

This is not at all strange, and fully predictable.

When the clock and data are exactly the same frequency, the Data will always have the same state at the rising edge of the clock, so no transitions will appear at the output. When the data frequency is half the clock frequency all transitions in the data will appear on the output, because the clock can "accurately sample" the data.

Then as you go lower, towards 0, you get less and less, not because of interference, but because the data signal just decreases in frequency. It still gets to the output just fine, because the clock can "easily sample" the data.

The reason the pattern is repeated, is because it is a purely digital system, so at each clock transition the data is sampled, and what ever is seen on the input is set at the output. If the data transitions exactly twice per one clock transition (double the frequency) the sample point will still always see the same data level at the rising clock edge, so again no output transitions are present. But at exactly three data transitions per clock, the data will again exactly toggle between each rising clock edge, again giving a maximum.

Etc etc etc.

So, aliasing.