Okay so I know when I need to build a parallel design I can put them near each other and make a 4k*8 to expand the databus. But on this one I only need to use half of them and the databus length is larger than my total chips can reach. But I thought 2k*12 requires 24k b of data and i have 32k of space to store data. So there has to be a way to do so.
When I use a parallel design I can reach 4k*8 but it is not enough.
The only way to increase the apparent width of a physical memory is to wrap it in a sequential circuit that executes multiple cycles internally for each external read or write cycle. This requires a means of multiplexing the data during write cycles and demultiplexing it during read cycles.
For example, you could turn your 4k × 8 physical memory into a 2k × 16 virtual memory by storing each 16-bit word in two consecutive 8-bit locations in the physical memory. The physical memory would execute two read or write cycles internally for each external cycle.
