Constant Bit Signal in VHDL

Question

I need to declare a bit with the constant value of 1.

What almost worked was:

signal name: bit := '1';

but the value of "name" is always '0' in this case.

How can I do this properly?

Full code:

ENTITY sleA IS
PORT(
    signal sel: std_logic; 
    A: in bit_vector (3 downto 0);
    S: out bit_vector (3 downto 0)
);
end sleA;
architecture arq_sleA of sleA is
begin
    sel <= '1';
    S(3) <= ((not sel) and A(3)) or (sel and A(2));
    S(2) <= ((not sel) and A(2)) or (sel and A(1));
    S(1) <= ((not sel) and A(1)) or (sel and A(0));
    S(0) <= ((not sel) and A(0)) or (sel and sel);
end arq_sleA;

Answer 1

If sel is an input for the entity then you can set the initial value in the entity's port:

port(
  sel: in std_logic := '1';
  A: in bit_vector (3 downto 0);
  S: out bit_vector (3 downto 0)
);

This will work in simulation, but for synthesis make sure your target technology supports initial "power-on" values (true for FPGAs, not so for ASICs). See Is initialization necessary?

Also note that signal is only used in the architecture body, not entity declaration.

Answer 2

If you want to use this entity always with a fixed value for sel, then remove the input port sel and declare a constant sel inside the architecture instead.

entity sleA is
port(
    A: in bit_vector (3 downto 0);
    S: out bit_vector (3 downto 0)
);
end sleA;
architecture arq_sleA of sleA is
    constant sel : std_logic := '1';
begin
    S(3) <= ((not sel) and A(3)) or (sel and A(2));
    S(2) <= ((not sel) and A(2)) or (sel and A(1));
    S(1) <= ((not sel) and A(1)) or (sel and A(0));
    S(0) <= ((not sel) and A(0)) or (sel and sel);
end arq_sleA;

If you want to use this entity several times with a different value for sel, then the input port must be kept (remove signal keyword). But, if you want to synthesize this unit also as a top-module with a fixed value for sel, instantiate it in a wrapper:

entity sleA_wrapper is
port(
    A: in bit_vector (3 downto 0);
    S: out bit_vector (3 downto 0)
);
end sleA_wrapper;
architecture rtl of sleA_wrapper is
    inst : entity work.sleA port map(sel => '1', A => A, S => S);
end rtl;

Now set this wrapper as the top-module for simulation and synthesis.