I need to declare a bit with the constant value of 1.
What almost worked was:
signal name: bit := '1';
but the value of "name" is always '0' in this case.
How can I do this properly?
Full code:
ENTITY sleA IS
PORT(
signal sel: std_logic;
A: in bit_vector (3 downto 0);
S: out bit_vector (3 downto 0)
);
end sleA;
architecture arq_sleA of sleA is
begin
sel <= '1';
S(3) <= ((not sel) and A(3)) or (sel and A(2));
S(2) <= ((not sel) and A(2)) or (sel and A(1));
S(1) <= ((not sel) and A(1)) or (sel and A(0));
S(0) <= ((not sel) and A(0)) or (sel and sel);
end arq_sleA;
constant name : bit := '1';
\$\endgroup\$sel
? A signal based solution:signal mySignal : std_logic;
mySignal <= '1'; \$\endgroup\$