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In my digital electronics labs and lectures we are told to try and make things from NAND gates, because they are the cheapest kind of gate available to buy. Why is this? Why isn't an OR/AND gate the cheapest to buy?

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I'm not sure your premise is correct. You aren't told to make things from NAND gates because they're cheap; you're told to do so because it's instructive. No one would ever build inverters on a chip out of NAND gates, they'd just build inverters. I doubt the DIP packages are much cheaper, either. –  endolith Oct 13 '11 at 21:55
    
@endolith No I asked the reasoning behind the question(hate having to answer questions that have no meaning) and this was one of the reasons I was given but it left me thinking. –  Dean Oct 14 '11 at 1:47
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The modern way to design digital systems is to write a behavioral specification (in VHDL or verilog) and let the synthesis tools worry about the gates to use. –  drxzcl Jul 23 '12 at 14:34
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6 Answers 6

up vote 18 down vote accepted

NAND gates are cheap because there are so many of them lying around from the 1980s.

Seriously though, a NAND gate is about the simplest logic gate. You can think of it as a multi-input inverter. Electrically, that's exactly what TTL NAND gates are. Each input is just another emitter added to the input transistor. The rest of the circuit is just a inverter. It's different in CMOS, but a NAND gate is still very simple.

Since the chips require few transistors, they can be small, which allows lots of them per silicon wafer, which makes them cheap.

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+1 for the fewest transistors. While not the cost driver they used to be this why NANDs cost less then other basic logic chips like AND and OR gates. –  Jim C Oct 14 '11 at 12:42
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In CMOS, a NOT gate is 2 transistors (the least transistor-cost gate), NAND and NOR require 4 transistors. Any other gates require 6 transistors or more. –  Arturo Gurrola Oct 23 '11 at 3:41
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@JimC: that still doesn't explain why NORs aren't used (if that's a fact). They have the same fewest number of transistors. –  Federico Russo Jul 23 '12 at 11:16
    
@romkyns answer addressed the reasons why NORs aren't used which makes it a better answer than this one. Because equivalent current PMOSs are ~double the size of NMOSs, the topology of an CMOS NAND lends itself to a smaller area than a CMOS NOR. See here for the NAND and NOR CMOS topology: iclayoutonline.com/Education/CMOSIntro/intropart4.asp –  horta Apr 9 at 17:36
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One of the reasons this may be said is that in CMOS circuits, a NAND gate is both smaller, area-wise, and faster than a NOR gate, whereas AND and OR gates require an explicit inverter circuit which is comparable in size to NAND/NOR. So in CMOS, NAND is a tiny bit cheaper.

This is not true of nMOS (it's the other way round there), and most certainly doesn't apply to packaged gates like the 74x series - the area cost is completely eclipsed by the cost of packaging and other overheads.

Reference: VLSI Design by Peter Robinson, p.14, "In CMOS, the NAND gate has better speed and area characteristics than the NOR gate".

Reference 2: here, paraphrased: "In CMOS, the NOR gate has two pMOS in series making it slower due to the poor mobility of the holes."

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A NOR is just a NAND upside down. It's not larger, nor slower. –  Federico Russo Jul 23 '12 at 11:18
    
@FedericoRusso Added a reference to support my claim. Mind you, the main point of this answer was to compare NAND/NOR to AND/OR, not NAND to NOR. –  romkyns Jul 23 '12 at 13:14
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@FedericoRusso: Suppose that an inverter would require an NMOS transistor of size 1 and a PMOS transistor of size 2 to achieve a desired switching speed. A two-input NAND gate of equal speed would require two (parallel-wired) PMOS gates of size two and two (series-wired) NMOS gates of size 2 (total size 8). A two-input NOR gate would require two series-wired PMOS gates of size 4 and two parallel-wired NMOS gates of size 2 (total size 12). –  supercat Jul 23 '12 at 19:25
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Any logical function can be built from NAND (or NOR) gates, even complete systems. OR and AND gates cost about the same as NANDs, but you need inverters as well. 1,000 NAND gates will be cheaper than a mixture of ORs, ANDs and inverters.

Seymour Cray used to build his Cray super-computers from ECL NOR gates for that reason.

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A few points not yet mentioned:

  1. In TTL logic, which used to be the "normal" type before MOS-based logic totally took over, a two-input NAND gate requires four transistors, one of which has two emitters; a two-input NOR gate would require six transistors (each with one emitter). More generally, an N-input NAND gate would require four transistors, one of which has N emitters; an N-input NOR gate would require 2N+2 transistors.
  2. In NMOS logic, an N-input gate, whether NAND, NOR, or some combination thereof (with only a single inversion, at the end) would require N transistors and one resistor. In NMOS, NOR gates are slightly faster than NAND gates.
  3. In CMOS logic, an N-input gate, whether NAND, NOR, or some combination thereof (with only a single inversion, at the end) would generally require N PMOS transistors and N NMOS transistors. A NAND gate will be slightly faster to output a "high" than will a NOR gate, with the difference becoming more pronounced as the number of input increases. A NOR gate, however, will be slightly faster to output a "low" than will a NAND gate. Since CMOS technology is, all else being equal, slightly slower to output high signals than low ones, a NAND gate may have somewhat more "balanced" output times.
  4. In most CPLD designs, the fundamental logic block consists of a bunch of many-input NAND gates (where inputs may be connected or disconnected) whose outputs drive a bunch of many-input NAND gates. Note that documentation generally shows a bunch of "AND"'s driving a bunch of "OR"'s, but NANDs driving NANDs will yield the same behavior as ANDs driving ORs, but with fewer inversions, since a NAND gate is not only an an AND with an inverted output, but behaves the same as an OR with inverted inputs. Son take the ANDs and ORs, invert the outputs of the ANDs and the inputs of the ORs (which one can do, since the two inversions cancel), and one is left with NANDs driving NANDs.

Any logic design which doesn't desire three-state logic or optimal speed can be implemented entirely with NAND gates. That isn't to suggest that NAND gates are always the most practical way of implementing things. An exclusive-or gate, for example, would take four two-input NAND gates to build, representing a total of sixteen transistors in CMOS. If one builds a CMOS exclusive-OR gate directly out of transistors, however, the job may be done with eight.

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I seem to remember there is a natural inversion. So an AND gate would need an extra inverter but the NAND does not. Or I could be wrong...

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There is an extra inversion, but one can build combinations of "and" and "or" gates with just a single inversion at the end. For example, one could build a CMOS gate to compute not((A and B) or (B and C) or (A and C)), with a single inversion, using six P-channel FETs (to generate the output "true") and six N-channel FETs (to generate the output "false"). Actually, one could do the job with five transistors, though analysis of the resulting circuit would be more difficult. –  supercat Oct 18 '11 at 19:25
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As well as being simple, NAND gates can be used in the place of all other gates, therefore, when companies buy in bulk, they buy only NAND gates because they can be used for everything. This saves them storage space and cheaper in bulk. Therefore, producers follow trend - more demand allows them to decrease price to increase future profits.

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This doesn't add anything that wasn't already said in previous answers. –  The Photon Dec 6 '12 at 17:07
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