Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It's 100% free.

Sign up
Here's how it works:
  1. Anybody can ask a question
  2. Anybody can answer
  3. The best answers are voted up and rise to the top

On Page 7 of the datasheet for M74HC590

It uses a CL (pF)

At the bottom of Page 8 is the test circuit which shows where the CL(pF) goes, in regards to a circuit diagram, but I don't understand that circuit diagram. Is the D.U.T. the chip they are testing?

For context what I'd like to do when I get these chips is put 4 of them in series to count the amount of time it takes sound to go from one ultrasonic transducer to another with as high of accuracy as I can.

So I can calculate the speed of air traveling through a pipe so I can know the volume of air traveling through it, In the volume of 1-200 Liter per minute hopefully with a resolution greater than .1 LPM through a 1" PVC pipe.

I could probably go smaller but I am limited by the blower blowing the air to have at least 2 Kpa with a minimum of 200 LPM and I don't have any information on how the flow will drop as the pressure increases. So I'm worried if I go too small on the pipe I'll get to much of a pressure drop before I get to the outlet where I need that much pressure.

240 LPM @ 32k RPM 4.5A 0 Pressure vs At Zero flow 5Kpa of pressure 1.6A 36k RPM Is the blower output

Side Question

share|improve this question
up vote 4 down vote accepted

For the test conditions part of your question, CL is a specific test load applied to each output to measure parametric data, and a different load is used for different tests.

DUT is indeed the Device Under Test.

At the test circuit, there is a note:

CL = 50pF/150pF or equivalent (includes jig and probe capacitance).

Looking at the device parameters (page 7 in particular), under Test Conditions, you will see CL. Note that the propagation delay and the high impedance to output valid timings are tested with load capacitances of both 50pF and 150pF, with (expected) longer timings with a higher capacitance load.

All other tests are measured with a 50pF total load.

An interesting parameter that you ignore at your peril is in the recommended operating conditions:

Input Rise and Fall Time. There are maximum times listed. This is very well explained in a TI application note, and is a well known issue in CMOS devices.

[Updated for application use]

To use these together, I would operate the counter clocks synchronously (i.e. the counter clock for all the stages is the same clock) and use the application suggestion in the datasheet for gating using the RCO to CCKEN for each subsequent stage.

There will be some timing uncertainty in your measurement results due to the propagation delay from clock to output Q(n) changing state.

The maximum frequency you can run at in cascaded mode is determined by the propagation delay (max) from CCK to RCO (upstream output) and the input setup time (min) of CCKEN to CCK (downstream input)

Together, these have a worst case timing of 80 nanoseconds. That yields Fmax of 12.5MHz

share|improve this answer
I see the maximum recommended input rise and fall time is 400ns @ 5v My plan for the counter was going to be to let them run, the signal to the transducer act as the register clock to output the current number of steps, record that, and then have the receiver also trigger the register clock and then read that as well, which would give me the Time it took to get from one to the other. – HilarieAK Jan 12 at 13:01
I read through that aplication note and I am confused as to where the problem would be. [Unfinished comment I tried to hit enter as a paragraph] – HilarieAK Jan 13 at 7:25
I read through that application note and I am confused as to where the problem would be. The RCO has a rise and fall time much faster than 400ns. Wouldn't I be able to make the RCO of 1 chip the CCK of the next chip? Then when I want the current count Rise up on the RCK faster than 400ns? AKA the first clock will be counting at 40MHZ the second will be counting at 40 MHZ / (28) the third will be counting at (40MHZ/(28))/2**8 and so on, if I put a pull down resistor wont that make sure any capacitance in the wires connecting them wont let the input fall too slowly? – HilarieAK Jan 13 at 8:02

That's a digital chip, which means its outputs ideally transition instantaneously from one state to the other. Capacitance on one of these outputs slows down the edges. They are telling you either the capacitance they did the tests with, or the maximum capacitance you can hang on a output and still have the chip perform according to the rest of the specifications.

You should not add any deliberate capacitance. Some unintentional capacitance will be unavoidable. This is telling you how much of such capacitance is OK.

share|improve this answer

Yes DUT is 'Device Under Test' - The circuit is just representative of the test circuit used to measure the timing waveforms shown on the next page, and CL is just the capacitance of the test probe - you don't have to add this in your application.

share|improve this answer

Your Answer


By posting your answer, you agree to the privacy policy and terms of service.

Not the answer you're looking for? Browse other questions tagged or ask your own question.