How can I increase the number of hardware UARTs in a design with a single UART MCU?

Question

I am using a TI CC430 MCU because it contains an embedded CC1101 radio frontend. I would really like to stick with this MCU. However, I need to simultaneously interact with a separate serial radio, a FTDI (uart->USB), and an RS232 GPS. So it would be nice to have 3 separate UARTS on the MCU.

What are my options for increasing the number of UARTs? I have considered adding a CPLD and muxing the single UART to 3 outputs, but I really don't like that approach because it not really 3 simultaneous connections.

Answer 1

You could add an extra UART over SPI or I2C. These have internal FIFO buffers inside them so you periodically check them for content and let them handle some buffering. NXP, TI, Maxim probably offer these parts. MAX3100, SC16IS752 etc. You could also add a second MCU to do this, but as you're already using quite a simple microcontroller with 1 UART and want to stick to that, that seems overkill.

You could also use a multiplexer to choose between the UART your micro talks to. But as you mentoined data is transmitted simultaneously , that won't work.

Software serial could be your last option but it can be very annoying to deal with if your microcontroller is doing other stuff as well.

Answer 2

If you have the pins available you can "bit blast", or do "Software Serial".

This is where you program the MCU to emulate a serial connection using simple GPIO lines.

The code is timing critical, so care has to be taken while writing it. There are various tutorials online about writing it, but it isn't something I have ever tried on an MSP430 chip, so I don't know the ins and outs of it.

The other option would be to use an external serial device which connects to the MCU through some other system, like SPI or I²C. I don't know what is available on this front - maybe another MCU running as an SPI slave device would do the job?

Answer 3

You might find the parallel version of the FTDI chip to be more useful even if you have to use shift-registers or a CPLD to reduce your I/O requirements. In one application of mine, I used a CPLD to connect an FTDI chip and some other things to a 3-wire bus (clk, mcu-data-out, and mcu-data-in). All wires are low when idle. Two rising edges on mcu-data-out while clock is low will reset the bus. When clk is low and data are both low, mcu-data-in will indicate whether there's anything that needs the CPU's attention. When clk is low and mcu-data is high, mcu-data-in will indicate whether the last operation was successful. When clk is high, mcu-data-in will supply data as expected by an SPI tranceiver.

One advantage of using the parallel version of the FTDI chip in this fashion is that you can have your CPU wake up when data becomes available, and then read out the data quickly. With the serial version of the FTDI chip, you must be ready to receive data whenever CTS is asserted, but you won't find out that data is available when CTS is de-asserted. I wonder whose ear I'd have to whisper in at FTDI to make them add such a feature to the serial version of their chip, or else add a mode similar to by three-wire mode?