You might find the parallel version of the FTDI chip to be more useful even if you have to use shift-registers or a CPLD to reduce your I/O requirements. In one application of mine, I used a CPLD to connect an FTDI chip and some other things to a 3-wire bus (clk, mcu-data-out, and mcu-data-in). All wires are low when idle. Two rising edges on mcu-data-out while clock is low will reset the bus. When clk is low and data are both low, mcu-data-in will indicate whether there's anything that needs the CPU's attention. When clk is low and mcu-data is high, mcu-data-in will indicate whether the last operation was successful. When clk is high, mcu-data-in will supply data as expected by an SPI tranceiver.
One advantage of using the parallel version of the FTDI chip in this fashion is that you can have your CPU wake up when data becomes available, and then read out the data quickly. With the serial version of the FTDI chip, you must be ready to receive data whenever CTS is asserted, but you won't find out that data is available when CTS is de-asserted. I wonder whose ear I'd have to whisper in at FTDI to make them add such a feature to the serial version of their chip, or else add a mode similar to by three-wire mode?