Take the 2-minute tour ×
Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It's 100% free, no registration required.

I am studying 8085 microprocessor architecture and the word edge triggered and level triggered confusing me really very much. Can anyone explain me it in layman's words ?

While studying the interrupts of 8085 named RST 7.5, RST 6.5, RST 5.5 and TRAP i came across these words and they confused me. Here i have attached one document link from which i was reading and i have mentioned my confusion diagrams.

in the document RST 7.5 -> Edge triggered RST 5.5 -> Level triggered. TRAP -> Edge triggered and Level triggered. (why ? does it make any difference?).

the document link

share|improve this question
    
That's not a pdf. –  starblue Nov 6 '11 at 11:55
    
yes, it is link to the pdf document. i have made correct changes. –  ankur.trapasiya Nov 6 '11 at 12:08
add comment

3 Answers 3

I didn't read you document really, but I can understand why you are confused. But it is a very simple concept really. Let me explain.

Triggering: This means making a circuit active. Making a circuit active means allowing the circuit to take input and give output. Like for example supposed we have a flip-flop. When the circuit is not triggered, even if you give some input data, it will not change the data stored inside the flip-flop nor will it change the output Q or Q'. Now there are basically two types of triggering. The triggering is given in form of a clock pulse or gating signal. Depending upon the type of triggering mechanism used, the circuit will become active at specific states of the clock pulse.

  1. Level Triggering: In level triggering the circuit will become active when the gating or clock pulse is on a particular level. This level is decided by the designer. We can have a negative level triggering in which the circuit is active when the clock signal is low or a positive level triggering in which the circuit is active when the clock signal is high.

  2. Edge Triggering: In edge triggering the circuit becomes active at negative or positive edge of the clock signal. For example if the circuit is positive edge triggered, it will take input at exactly the time in which the clock signal goes from low to high. Similarly input is taken at exactly the time in which the clock signal goes from high to low in negative edge triggering. But keep in mind after the the input, it can be processed in all the time till the next input is taken.

That is the general description of the triggering mechanisms and those also apply to the 8085 interrupts.

share|improve this answer
    
well .. regarding edge triggering, usually you have to have the data stable for a short while for at least a specific amount of time before the edge (consult data sheets) and keep it stable for a certain length of time (consult data sheets) but these times are usually pretty short. –  JustJeff Nov 7 '11 at 0:44
    
i understand what you wanted to explain but one another question that i have mentioned is in 8085 TRAP is both edge triggered and level triggered(see the document). So what is the functionality in such a case when circuit is both level sensitive and edge triggered. –  ankur.trapasiya Nov 7 '11 at 6:54
    
In that case it wants the edge to also go past a certain level. So we need something like rising edge and level > 3V –  Steven Goldade Dec 28 '12 at 17:22
add comment

On an 8085, TRAP is a non-maskable interrupt normally used to handle errors such as a power failure.

If it were level triggered, its code could never execute because it's an unmaskable interrupt. The handler would start executing when it became active, but it would still be active, so the handler would start executing, but it would still be active, so the handler would start executing, etc., etc. Therefore it has to be edge triggered.

However, edge triggering is a problem when the line may have glitches. Glitches may cause the handler to be invoked multiple time as the line glitches. It's a very big problem with TRAP since it is non-maskable and results in a RST.

As a compromise, the TRAP works as if it is level triggered, except that it is only recognized when it has been low since the last time it was recognized. That ensures that the TRAP handler is only invoked once.

This is what they mean by "edge triggered and level triggered".

share|improve this answer
add comment

*Triggering* means making a circuit active. In level triggering the circuit will become active when the gating or clock pulse is on a particular level. In edge triggering the circuit becomes active at negative or positive edge of the clock signal.

share|improve this answer
3  
This is pretty much what was said above. –  Brian Carlton Oct 11 '12 at 19:54
add comment

Your Answer

 
discard

By posting your answer, you agree to the privacy policy and terms of service.

Not the answer you're looking for? Browse other questions tagged or ask your own question.