Take the 2-minute tour ×
Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It's 100% free, no registration required.

Is Nios II required when implementing UART core using the SOPC? (or a default Nios is included) I tried writing my own module for the uart connection but it didn't work out. I need a method to connect a sensor to the de2, any method is fine. If you guys could give a clear method about how can this be implemented

This link gives an idea what could be done but its not that clear

I need a idea on how to go about it. With so many manuals and softwares available for the Altera..

share|improve this question
    
possible duplicate of De2 Board reading sensor reading –  Brian Carlton Nov 17 '11 at 20:00
    
No. A UART is basically a state machine. Though if your data to be transmitted or received gets more complicated than you want to handle in a state machine, you might start to consider some sort of soft processor core. That said, while UARTs are very doable, SPI-type interfaces are simpler to implement, so if not dictated by what is on the other end, you might consider that. –  Chris Stratton Jul 13 '12 at 14:31
add comment

1 Answer

The following links MAY be of use to you.
Zero guarantees.

DE2 Hyerterminal wannabe

RS232 from scales wannabe

UART / DE2 with links elsewhere

This looks useful Altera UART core overview. Chapter 8 in vaguely specified manual.

Do you have / are you using SOPC builder?
It SOUNDs to do what you want

  • The universal asynchronous receiver/transmitter core with Avalon® interface (UART core) implements a method to communicate serial character streams between an embedded system on an Altera® FPGA and an external device. The core implements the RS-232 protocol timing, and provides adjustable baud rate, parity, stop and data bits, and optional RTS/CTS flow control signals. The feature set is configurable, allowing designers to implement just the necessary functionality for a given system.

    The core provides a simple register-mapped Avalon Memory-Mapped (Avalon-MM) slave interface that allows Avalon-MM master peripherals (such as a Nios® II processor) to communicate with the core simply by reading and writing control and data registers.

    The UART core is SOPC Builder-ready and integrates easily into any SOPC Builder-generated system. This chapter contains the following sections:
    ■ “Functional Description” on page 8–2
    ■ “Device and Tools Support” on page 8–4
    ■ “Instantiating the Core in SOPC Builder” on page 8–4
    ■ “Hardware Simulation Considerations” on page 8–9
    ■ “Software Programming Model” on page 8–9

One level up above chapter plus many other modules

Using the DE2 JTAG UART about page 9 on.

share|improve this answer
    
lol. "zero guarantees". enjoy much your comments on links, lol. –  abdullah kahraman Dec 16 '11 at 8:28
add comment

Your Answer

 
discard

By posting your answer, you agree to the privacy policy and terms of service.

Not the answer you're looking for? Browse other questions tagged or ask your own question.