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In many tutorials regarding ARM CPU registers, the instruction register is mentioned in such way: "Register R15 in ARM micro-controller is the program counter and it points to the next instruction to be fetched from memory."

But I also read that in Harvard architecture, there is instruction memory and data memory. What I understood or misunderstood from this was the instruction codes are stored in flash ROM, and the data is stored in RAM.

But when I read more about it, I get the impression that the instructions also are fetched from RAM instead of ROM.

Does ROM have nothing to do with the whole operation besides storing the machine code?

edit: Question assumes no operating system, just a standalone ARM micro-controller.

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Harvard architecture is only used in "small-scale" devices like microctrollers or inside the CPUs themselves. Big architectures with vast amount of RAM never use full Harvard architectures – Lưu Vĩnh Phúc Mar 21 at 3:11

ARM cores are actually what is called modified Harvard architecture. In this case, ROM and RAM sit in the same address space, so an ARM processor can execute code out of either or access either as data. In the modified Harvard architecture, the processing core is directly connected to two separate instruction and data caches. This allows for high performance due to being able to access instructions and data simultaneously. At a high level the combined address space makes the whole system act like a Von Neumann architecture.

The structure of the address space is determined by the physical connections between the processing core itself and any memories and peripherals. For the most part the layout of the address space will be fixed with particular ranges corresponding to memory-mapped peripherals, mask ROM, Flash, RAM, etc. However, there may be some ability to remap certain sections of address space or to configure peripherals or external memories to sit in specific regions of the address space.

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Aha, there is a technical term for this: modified Harvard architecture: en.wikipedia.org/wiki/Modified_Harvard_architecture . – alex.forencich Mar 20 at 1:29
ROM and RAM can be in the same address space, but not (usually) in overlapping addresses in that space. In an ancient system I used (Intel 8085) ROM occupied addresses 0x0000 to 0x7fff, while RAM was at address 0x8000 - 0x9fff immediately following the end of ROM (we used 8KB RAM and ROM chips). In that system, the program code was in ROM (UVPROM, actually) and data was in RAM. – Peter Bennett Mar 20 at 1:33
The CPU instruction register can point anywhere in the address space. If it happens to point to RAM, then it will fetch instructions from RAM. If it happens to point to ROM, then it will fetch instructions from ROM. Now, it is entirely possible that your program will never direct execution into RAM, which is likely the case for many embedded ARM processors. – alex.forencich Mar 20 at 1:46
@user16307 Instructions can be fetched from ROM or RAM or anywhere else in the address space. – tangrs Mar 20 at 11:48
The processor core itself, does not know ram from rom from peripheral they are just addresses. the cortex-m does have some rules about what address ranges you can use for things, but it is the chip developer that determines where things actually are. As far as where instructions can live, they can live anywhere that the core is allowed to execute which may be as much as the entire address space. Naturally you have to boot from flash/rom as it is non-volitile but after that on an arm you can run from ram if you copy code there and branch to it – dwelch Mar 20 at 14:49

The ARM architecture is a von Neumann architecture, not a Harvard architecture. That means it uses a unified address space for both instructions and data. Whether any particular address contains RAM or ROM is up to the system designer. Instructions can be fetched from either.

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Do you mean EEPROM and RAM are both called as memory by saying "unified address space"? I thought data variables are stored in RAM and instructions are in ROM. What do you mean by system designer? – user16307 Mar 20 at 1:27
No, not all instructions are in ROM. The system designer is the guy who decides what kind of memory to use for what purpose in a given application. Some deeply-embedded ARMs will have all of their instructions in ROM, while others will have only a bootloader in ROM and load the actual application code from secondary storage of some sort into RAM. The advantage is that RAM can be much faster than ROM in many cases. – Dave Tweed Mar 20 at 1:31
Just to be sure "system designer" is not the guy who writes a C code and compiles into the micro-controller right? He is the guy who designs the micro-controller itself? If so, I can find from the datasheet of the micro-controller whether the instructions are fetched from RAM or ROM? – user16307 Mar 20 at 1:36
@user16307 All ARM processors will be able to execute instructions from anywhere in their address space. If the ROM is mapped into the address space, then instructions can be executed from there. Same goes for RAM. The only case where you wouldn't be able to execute code from ROM is if there is an MMU or NX bit that prevents access in the current context or if the ROM has to be accessed via a peripheral such as an SPI or SDIO/MMC controller, in which case the instructions would have to be copied into RAM first. – alex.forencich Mar 20 at 1:43
In general, yes. Usually the code gets loaded into something non-volatile. However, in some cases that non-volatile memory may not be memory-mapped, so you cannot execute out of it. Some chips have a bootloader in mask ROM (cannot be modified after the chip is produced) that is responsible for loading code from an external memory such as an SPI flash chip, SD card, etc., possibly decompressing or decrypting it, copying it into RAM, and executing it. – alex.forencich Mar 20 at 2:07

ARM microcontrollers, the newer Cortex-M ones, have modes to operate either from RAM or ROM. Check, for example, BOOT0 and BOOT1 bits in STM32's Reference Manual. This pretty much configures the start address of execution by actually aliasing the actual memory addresses into a fixed memory address segment (0x0000 0000 to 0x0007 FFFF).

The Cortex-M core has four types of "memory": RAM, ROM (flash and System Memory), FSMC and peripheral. RAM is, well, internal static RAM. ROM is internal flash or the unwritable embedded bootloader. FSMC allows using external memory (both RAM and ROM, depending what the external hardware is). Peripheral memory are specific registers that map to peripheral functions, like UARTs, ADCs, etc. The hardware to access them is separate to gain speed (Harvard-style), specially because flash is slower than SRAM.

Yet, all of those are unified in a single address space (Von Neumann-style), which makes access to them simplified from a programmer's perspective. They differ only by their address ranges (implementation-dependent). The BOOT pins allow configuration between three start addresses: one in RAM, one in ROM (read-only bootloader) and another one in ROM (flash). This makes it possible to answer your question as "both". I never tried, but it appears to be possible to jump from one segment to another.

Keep in mind, however, that those memories still cannot be dealt with equally. You can't arbitrarily write to ROM. It's flash, making them rewritable, but you must use a special procedure to write to them (it's usually called something like "using flash as EEPROM" to store program data, or "bootloader" when storing program code, usually at startup).

Curious info:

When one executes from flash (ROM), the instructions are retrieved directly from ROM. There's usually some startup code that copies data from ROM to RAM (initialized global variables, usually stored in the data section). The Reference Manual also carries this info

When booting from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register.

which is usually carried out by the startup code.

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The boot modes here clarify what is going on. The user can select (here with pin settings) the memory device that is read by code accesses to addresses 0x0 and 0x04 on reset. This is actually changing the address decoding, and yes, you can jump from 0x04 (reset vector) to 0x08000008 to be executing from the next instruction in flash, or to 0x20000000 to get to SRAM. – Sean Houlihane Mar 20 at 10:52
Usually on the smaller mcu devices, running code from FLASH is just as fast as running from SRAM or ROM. There might be library functions in masked ROM though (for space/cost reasons, or protection - and then data retches from the ROM would probably be blocked at the soc design level) – Sean Houlihane Mar 20 at 10:59
is opcode of the next instruction is at R15 always? – user16307 Mar 20 at 18:59

Regardless of the Architecture, R15 will hold the program counter address. The next (hopefully valid) instruction will be fetched from this (hopefully valid) address. Note that it is possible for either of these to be problematic.

1) invalid op codes. 2) Memory of any kind may not be installed for the address.

Yes it is desirable for areas reserved for data not to be executed as program code. The address space we speak of is bounded (it is not a windowed address space as used in PC's, midrange, mainframe etc.) and may contain RAM, ROM, Peripheral Ports.

It should certainly be possible to fetch instructions from RAM if we have RAM for the addresses we consider to be valid for instructions, so code can be loaded if we desire, overlay style. Even without an OS.

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