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I'm pretty new to embedded systems, and I keep seeing this term used all the time, but I can't quite understand what is it. A quick search online yields this Wikipedia page: https://en.wikipedia.org/wiki/Joint_Test_Action_Group which describe it as some-kind of protocol for debugging. But in other contexts it used like it's able to program a chip's memory like a programmer. What is it?

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There's some useful gems hidden in this question. – David Mar 27 at 13:44
I gave dwelch a +1. Additionally, JTAG is sometimes mis-used as a verb meaning, generically, "to debug/test" a thing. A person "JTAG'ing something" may actually be using a different protocol that the device's manufacturer has overlapped with the physical JTAG pins (i.e. SWD). You can SWD, or JTAG, but not both. Nobody SWD's ("swoods"?) their devices, though. – Jon Mar 28 at 2:27
Yeah you can program with JTAG – StevieV Mar 31 at 13:40
up vote 20 down vote accepted

It is like USB, SPI, I2C, and other "busses", and it has a number of popular uses, not limited to:

  • One in particular is in testing of silicon before too much is invested in each part, for example while a chip is still on the wafer you can check most of the part. Granted dicing the wafer can do damage so you want to test again but maybe you do that before packing, maybe after.

  • You can use it to do boundary scan on boards. You can take a board on a production line (granted the board has to be designed right and some percentage of the chips have to support this) but you can do low speed connectivity tests, stimulate the pin on one end of a trace and scan other parts to see that they are or are not connected per the design of the board.

  • Since the chips already have these dedicated pins why not, for processors, use that same interface as a way to talk to an on chip debugger (OCD), design something into the processor and allow that to be talked to via jtag.

It is a generic-ish way to allow you to isolate things on the chain you want to send a series of bits to or get a series of bits from, in a way that each thing you want to talk to can be designed for various numbers of bits from a small number to a large number. For a debugger you would naturally have it write to or read from a register-sized thing in your chip - maybe a 16 bit register or 32 bit. But for silicon or board testing your scan chain might be dozens of bits. Each individual thing you address can vary in size, if you want, from any other thing, making this a very versatile bus with a relatively small number of pins that is attractive for these types of use cases.

Perhaps because of the popularity for software debugging they now have some two pin solutions to save on pin count for microcontrollers and perhaps others will adopt that, perhaps not.

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Are there technical aspects of JTAG that lend it to these uses, or is it just for historical reasons? – Owen Mar 28 at 13:48
Well read the wikipedia article. My opinion is because it was already there and wired into the boards and chips, and because it was flexible enough to support other uses, and at least some already had tools in place, someone must have said why not use it for these other things. I think its flexibility vs pin count makes it very attractive. There are and continue to be other solutions for debuggers or in circuit programming but thanks to the FTDI MPSSE instructions and FTDI's success in general with everything USB, inexpensive jtag tools are now widely available. – dwelch Mar 28 at 14:15

JTAG was originally an interface used for testing PCBs after assembly. The IO lines on the chips could be controlled and read via the JTAG ports allowing a board test sequence to be performed. Later on it also started to be used as a programming and debug interface. What functionality is available over JTAG will depend on the particular IC you are dealing with.

One advantage of JTAG over most other programming interfaces is that devices can be daisy chained. So one JTAG port can serve to program/debug/test multiple devices (though I would advise designing your systems so that different brands of chip can be split on to different chains, while the low level JTAG protocol is pretty standardised unfortunately the tools you need to program/debug the chips are not).

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JTAG is somewhat an odd term. To begin, the term can specify a specific connector and protocol, composed of a clock signal (TCK), mode-select (TMS), and data in/out (TDI/TDO). This comprises a network of devices, where each device's TDO is connected to the next device's TDI in a so-called scan chain. TMS is used to put all devices simultaneously into various modes.

The devices on the scan chain are typically connected as one large shift register comprised of registers in each individual device. When devices are in the SHIFT_IR or SHIFT_DR state, they connect to the scan chain one of two temporary registers: An instruction register, and a data register.

Once a value is shifted in, the UPDATE_IR or UPDATE_DR mode can be activated by setting TMS appropriately while toggling TCK. At this point, the value shifted into the register "takes effect". For example, shifting various sequences into the IR of an FPGA and transitioning into UPDATE_IR will cause the FPGA to enter various modes such as configuration, readback, normal runtime, or access specific user registers and JTAG-specific primitives instantiated in the design.

Likewise, capture states can be used to "read" a value from the device and put it into the IR or DR, to be shifted out through TDO and ultimately read by the JTAG programmer.

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JTAG defines a serial protocol, and some commands, to allow access to internal registers within complex ICs. This allows a tester to get observability and controllability in a standard way using few pins.

The original use was for 'boundary scan', where all the I/O pins could be read and driven by a large shift register that circles the chip. However, it was quickly augmented to add further shift registers to access the internals of the chip, including memories.

You rarely bit-bang JTAG, access is usually through libraries, aka drivers, supplied by the IC manufacturer, and used by the test system and test access adapter.

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So the chip actually need to support a JTAG both by hardware and software? – UnTraDe Mar 27 at 14:21
@UnTraDe No, the chip supports JTAG in hardware and may in software (e.g. an FPGA may expose some interfaces between JTAG and the user design), but isn't required to have software support on the chip. The tools that one would use to interact with devices over JTAG would have both software and hardware support (software on a computer, and hardware in terms of a JTAG programmer attached to that computer) – hexafraction Mar 27 at 14:51

There is what JTAG 'means' and there is what JTAG 'is'. As others have pointed out JTAG 'is' a industry standard bus interface for manufacturing testing, as in Joint Test Action Group.

What JTAG 'means' to an embedded software developer is the debug interface on the SoC/microprocessor for external debug of embedded software running on the chip. Nearly every CPU/SoC on the market uses the JTAG interface not only for manufacturing tests, but for software debug support. You will find a JTAG interface on everything from server class x86 CPUs to under $50 home WiFi routers. With the right interface hardware, and the right software, these interfaces will grant you the ability to read/write memory, set breakpoints, and single-step code.

The key of course is getting the right hardware and software. Even though the basic JTAG interface is standardized, the specific software debug facilities available in a device may not be. JTAG is like TCP/IP. It exists in the middle of the application stack. You need the right physical layer to communicate with the equipment (i.e. what do you mean this thing uses 10-Base-2?!?!?), and you need the right application software above it (what do you mean I need a Gopher client?!?!?!). However the strength of the ARM ecosystem has lead some degree of standardization there (see OpenOCD).

You also asked about using JTAG to program flash. Yes, some software uses it for that purpose as well. The SoC may provide JTAG facilities to read/write from CPU memory address spaces, it may provide direct access to flash controllers, and at a minimum JTAG provides raw low-level access to I/O pins on the edge of the chip (this was the original purpose of JTAG, to enable continuity testing of chip to chip interconnections during manufacturing test, i.e. 'JTAG boundary scan'). Any of these facilities could be use by clever programmers to drive the signals necessary to reprogram a flash chip in case a device is accidentally 'bricked'.

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